{"id":183682,"url":"https://alion.io/job/espace-fpga-verification-engineer-avionics","title":"FPGA Verification Engineer - Avionics","company":{"id":2438005,"name":"E-Space","domain":"e-space.com","url":"https://alion.io/company/e-space-com","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"C","score":69,"open_postings":105,"ghost_share":0.505,"stale_share":0,"repost_share":0.038,"time_to_fill_p50_days":52,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Saratoga, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":150000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"CI/CD","optional":true},{"name":"Formal Verification","optional":true},{"name":"Python","optional":true},{"name":"Siemens QuestaSim","optional":true},{"name":"TCL Scripting","optional":true}],"status":"live","first_seen_at":"2026-04-02T22:46:04Z","employer_posted_date":"2026-04-02","last_verified_at":"2026-10-18T03:08:11Z","board_verified":true,"closed_at":null,"days_open":198,"trust":{"level":"ghost","repost_count":1,"flags":["stale","company_stale"],"days_open":197},"description":"We are hiring FPGA Verification Engineers to build and maintain the verification infrastructure for satellite avionics FPGA designs. You will develop UVM-based testbenches, create coverage-driven verification plans, and ensure RTL correctness for flight-critical FPGA firmware across multiple subsystems. This role is instrumental in establishing a rigorous verification methodology for the program.\nKey Responsibilities:\nDevelop UVM-based verification environments including agents, scoreboards, and bit-accurate reference models.\nCreate and maintain a reusable, extendable UVM framework supporting multiple FPGA targets and device configurations.\nWrite verification plans derived from requirements specifications and architectural documents.\nDevelop functional coverage models and drive coverage closure for all FPGA designs.\nPerform RTL simulation using industry-standard tools.\nImplement clock-domain crossing verification and timing/stability analysis.\nApply lint and static-analysis tools to identify design issues early in the development cycle.\nSupport hardware bring-up by creating tests that model and recreate hardware interactions in simulation.\nDocument verification results, coverage metrics, and test plans with clear technical writing.\nCollaborate with FPGA designers and system engineers to refine requirements and close verification gaps.\nRequired Qualifications:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n4+ years of experience in FPGA or ASIC verification.\nStrong expertise in SystemVerilog and UVM-based verification methodology.\nExperience building UVM agents, environments, and generating constrained-random stimulus.\nProficiency with at least one industry-standard RTL simulator.\nUnderstanding of functional coverage techniques and coverage-driven verification.\nAbility to read and understand PCB schematics and hardware interfaces for test development.\nPreferred Qualifications:\nExperience verifying designs for space, aerospace, or high-reliability applications.\nFamiliarity with formal verification tools.\nBackground in embedded software interaction with FPGA firmware.\nExperience with continuous integration workflows for verification regressions.\nProficiency in Python, TCL, or shell scripting for test automation and infrastructure.\nExposure to DFMEA and high-reliability digital design review processes.\nTools & Technologies:\nIndustry-standard RTL simulators (e.g., VCS, QuestaSim, or equivalent)\nUVM verification methodology\nLint and CDC analysis tools\nPython/TCL scripting for automation\nAdditional Requirements\nThis is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.","description_format":"text","description_chars":2744,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Space & Aerospace","Satellite Manufacturing"],"lifecycle":[{"event":"open","at":"2026-09-01T08:47:55Z"},{"event":"reopen","at":"2026-10-14T07:11:13Z"}],"visa":[],"liveness":{"score":8,"band":"cold","label":"Long shot","p_open":1,"p_active":0.278,"p_room":0.28,"age_days":197,"expected_fill_days":52,"reasons":["conf:0","stale_co","velocity","ghost","win:tail","crowd:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":{"stated_usd_annual":250000,"is_top_pay":true},"html_url":"https://alion.io/job/espace-fpga-verification-engineer-avionics","json_url":"https://alion.io/job/espace-fpga-verification-engineer-avionics.json","meta":{"generated_at":"2026-10-18T04:50:39Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7280,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":2438005},"rest":"https://alion.io/mcp/rest/get_company?id=2438005"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fespace-fpga-verification-engineer-avionics"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fespace-fpga-verification-engineer-avionics"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fespace-fpga-verification-engineer-avionics"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/espace-fpga-verification-engineer-avionics\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fespace-fpga-verification-engineer-avionics"}]}