{"id":183672,"url":"https://alion.io/job/espace-fpga-vlsi-engineer","title":"FPGA / VLSI Engineer","company":{"id":2438005,"name":"E-Space","domain":"e-space.com","url":"https://alion.io/company/e-space-com","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":71,"open_postings":106,"ghost_share":0.472,"stale_share":0,"repost_share":0.038,"time_to_fill_p50_days":52,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Saratoga, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":127000,"max_usd":286000,"period":"year","method":"role_country_seniority_unknown","sample_n":2844},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-05-06T18:07:03Z","employer_posted_date":"2026-05-06","last_verified_at":"2026-10-22T10:46:02Z","board_verified":true,"closed_at":null,"days_open":168,"trust":{"level":"ghost","repost_count":1,"flags":["stale","company_stale"],"days_open":168},"description":"We are seeking an FPGA/VLSI engineer to contribute to digital hardware development targeting ASIC/SoC platforms used in advanced communication systems. This role focuses on RTL design, FPGA prototyping, and system integration, working closely with cross-functional teams to deliver high-quality designs.\nResponsibilities:\nDesign and implement RTL using SystemVerilog with consideration for timing, power, and area\nPerform FPGA prototyping, validation, and hardware bring-up for digital designs\nDevelop and execute simulation and debugging strategies at block and subsystem levels\nContribute to SoC-level integration, including interfacing with processors, memory, and peripherals\nAnalyze and resolve timing issues, including setup/hold violations and basic clock domain crossing concerns\nCollaborate with verification, ASIC, and software teams to ensure functional correctness and performance\nParticipate in design reviews and contribute to improving design quality and best practices\nQualifications:\nBachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field\nStrong experience writing synthesizable SystemVerilog/Verilog\nProven experience with FPGA development flows, including synthesis, implementation, and validation\nSolid understanding of digital design fundamentals and timing analysis\nPreferred Skills:\nExperience with SoC FPGA platforms (e.g., Xilinx Zynq, Intel SoC FPGA)\nFamiliarity with AXI/AHB or similar bus protocols\nExposure to ASIC design flow, including synthesis and STA\nExperience with high-speed interfaces (e.g., PCIe, Ethernet)\nKnowledge of communication systems (e.g., 5G PHY/MAC concepts)\nWhat Success Looks Like:\nIndependently handles well-defined design blocks from RTL to FPGA validation\nProduces clean, efficient, and timing-aware RTL\nEffectively debugs issues across simulation and hardware\nCollaborates well within a team and contributes to overall project progress\nContinuously improves technical depth and delivery efficiency\nAdditional Requirements\nThis is a fast-paced, high-impact environment - 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