Senior DV Engineer

We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work.

Requirements

• HDL & Verification Methodology

  · Proficiency in Verilog and SystemVerilog

  · Working knowledge of UVM architecture and methodology

  · Ability to write verification tests within an existing environment

  Programming & Scripting

  · Some experience scripting in Perl, Python, or bash

What you bring to this role:

• 4+ years of design verification experience in the semiconductor industry

Additional Requirements

This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.