{"id":183668,"url":"https://alion.io/job/espace-senior-static-timing-analysis-sta-methodology-engineer","title":"Senior Static Timing Analysis (STA) Methodology Engineer","company":{"id":2438005,"name":"E-Space","domain":"e-space.com","url":"https://alion.io/company/e-space-com","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":80,"open_postings":95,"ghost_share":0.242,"stale_share":0,"repost_share":0.053,"time_to_fill_p50_days":83,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":118000,"max_usd":223000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":6333},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-05-06T20:17:29Z","employer_posted_date":"2026-05-06","last_verified_at":"2026-11-08T03:07:09Z","board_verified":true,"closed_at":null,"days_open":185,"trust":{"level":"ok","repost_count":2,"flags":["repost","company_stale"],"days_open":184},"description":"We are seeking a Senior STA Methodology Engineer to join our ASIC design team. In this role, you will own cross-functional timing methodology efforts across multiple IPs, projects, and technology nodes for our cutting-edge SoC designs targeting 5G, IoT, and LEO satellite communication applications. You will architect and maintain production STA flows, drive signoff closure, and introduce data-driven techniques to continuously improve PPA and team productivity.\nWHAT YOU WILL BE DOING:\nLead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes\nDevelop and enhance STA methodologies across the full RTL-to-GDS flow, including early timing estimation, feasibility checks, synthesis and place-and-route optimization, signoff criteria, and post-route ECO strategies\nArchitect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA and runtime efficiency\nDrive signoff correlation and closure using PrimeTime and related tools (PT-SI, PTPX, PT-ECO)\nDebug timing constraints, resolve timing correlation issues, and develop effective timing closure strategies\nExplore and deploy data-driven and ML-assisted techniques to improve STA automation, predict and prioritize timing risk, and guide optimization across blocks and full-chip\nDesign, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity\nContinuously refine workflows and introduce new technologies to ensure robust, PPA-optimized timing solutions across all product lines\nProvide timing closure guidance and mentorship to design and physical design engineers\nWHAT YOU BRING TO THIS ROLE:\nBS or MS in Electrical or Computer Engineering, or equivalent industry experience\n8+ years of industry experience in STA and timing methodology, focused on high-performance and low-power designs at advanced technology nodes\nDeep knowledge of STA tools and techniques, including noise, crosstalk, OCV, AOCV, POCV, and LVF analysis\nFluency with PrimeTime and related signoff tools (PT-SI, PTPX, PT-ECO), with extensive hands-on experience driving signoff correlation and closure\nStrong expertise in debugging timing constraints and resolving timing correlation issues across complex SoC designs\nExperience with MMMC analysis, timing ECO flows, and late-stage timing closure techniques\nProficiency in writing robust, production-quality scripts in Tcl, Python, and/or Perl for CAD utilities and flow components\nSolid knowledge of clock tree synthesis (CTS) and its interaction with timing analysis\nExcellent communication and collaboration skills for cross-functional, multi-project environments\nBONUS POINTS:\nExperience with advanced process nodes (7nm, 5nm, or below)\nFamiliarity with low-power design methodologies and their timing implications (DVFS, power gating)\nExposure to interface protocol timing (DDR, PCIe, USB, SerDes)\nExperience applying ML or data-driven methods to EDA flow optimization\nBackground in satellite communication, 5G, or IoT SoC design\nAdditional Requirements\nThis is a fast-paced, high-impact environment - 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