{"id":183676,"url":"https://alion.io/job/espace-soc-platform-engineer","title":"Silicon Platform Engineer","company":{"id":2438005,"name":"E-Space","domain":"e-space.com","url":"https://alion.io/company/e-space-com","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"C","score":68,"open_postings":106,"ghost_share":0.519,"stale_share":0,"repost_share":0.038,"time_to_fill_p50_days":52,"computed_at":"2026-10-20T05:45:00Z"}},"role":"DevOps","role_family":"DevOps","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":128000,"max_usd":283000,"period":"year","method":"role_country_seniority_unknown","sample_n":4161},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Git","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"VHDL","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-05-01T22:58:44Z","employer_posted_date":"2026-05-01","last_verified_at":"2026-10-20T22:15:40Z","board_verified":true,"closed_at":null,"days_open":172,"trust":{"level":"ghost","repost_count":1,"flags":["stale","company_stale"],"days_open":171},"description":"We are seeking a skilled and driven Silicon Platform Engineer to join the System-on-Chip platform team that works on IP integration, chip-level verification, and firmware development. This is a System-on-Chip design, integration and verification role, working at the intersection of hardware and software. You will shape the platform from IP bring-up through full-chip validation: defining testbenches, authoring test firmware, and implementing critical chip features in silicon. This is a hands-on role with broad impact across the hardware development cycle.\nCore Responsibilities\nIP Integration and Verification\n- IP Integration: Evaluate, integrate, and verify IP blocks within the chip, ensuring correct connectivity, configuration, and interoperability across the platform.\n- Feature and Module Firmware: Author targeted test firmware to bring up and verify individual IP blocks and hardware features at the module level.\n- Subsystem Firmware: Develop subsystem-level test firmware to validate interactions between integrated components and confirm correct system behavior across hardware boundaries.\nTestbench Development and Build Flows\n- Testbench Infrastructure: Define, implement, and maintain system-level testbenches covering subsystem and full-chip verification scenarios.\n- Build Flow Management: Own and manage testbench build flows, ensuring reproducibility, scalability, and integration with the broader verification environment.\nChip Feature Implementation\n- Hardware Security: Implement chip-level security features, including secure boot, hardware root of trust, and cryptographic accelerator integration.\n- Inter-Subsystem Communication: Define and implement communication fabrics and protocols between chip subsystems, including AMBA-based interconnects (AXI, AHB, APB).\n- Power Management: Implement hardware power management features, including power domain control, clock gating, and low-power state transitions.\n- Boot Flow and Configuration: Define and implement the chip boot architecture, including reset sequencing, configuration registers, and boot ROM integration.\n\nWhat you bring to this role:\nHardware Description Languages: Proficiency in RTL design and verification using SystemVerilog and/or VHDL.\nVerification Methodologies: Experience with UVM or similar structured verification methodologies.\nFirmware Development: Ability to write bare-metal C firmware for hardware bring-up, feature validation, and test automation on embedded targets.\n AMBA Interconnects: Strong knowledge of AMBA protocols (AXI, AHB, APB) and their application in chip integration.\nChip Architecture: Understanding of subsystem partitioning, memory maps, interrupt routing, and hardware/software interfaces.\n Debugging Tools: Experience with simulation tools (e.g., VCS, Questa, Xcelium) and hardware debug environments (JTAG, logic analyzers, oscilloscopes).\nScripting: Proficiency in scripting languages such as Python, Tcl, Bash, and Makefiles for build flow automation and test infrastructure.\n Version Control: Expertise with Git or similar version control systems.\nBonus points for the following:\n- Experience with ARM Corstone reference designs and Cortex-M or Cortex-A processor integration.\n- Familiarity with TrustedFirmware-M, MCUboot, or PSA-certified security architectures.\n- Knowledge of embedded security concepts, including cryptographic algorithms and Post-Quantum Cryptography (PQC).\n- Experience with formal verification or property checking tools.\n- Familiarity with FPGA emulation platforms for pre-silicon validation.\n- Knowledge of 3GPP network protocols as they relate to modem or connectivity subsystem integration.\n- Experience with low-power chip design and power intent methodologies (UPF/CPF).\n- Familiarity with Cortex-A and Cortex-M class processors, NPU processors, and DSP processors.\n- Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\nCollaboration and Documentation:\n· Cross-Functional Partnership: Work closely with Silicon firmware engineers, RTL designers, and physical design teams to ensure cohesive hardware-software integration throughout the development cycle.\n· Documentation: Produce and maintain clear technical documentation covering integration specifications, verification plans, test procedures, and feature implementation details.\nAdditional Requirements\nThis is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.","description_format":"text","description_chars":4524,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Space & Aerospace","Satellite Manufacturing"],"lifecycle":[{"event":"open","at":"2026-09-01T08:47:55Z"},{"event":"reopen","at":"2026-10-14T07:11:13Z"}],"visa":[],"liveness":{"score":7,"band":"cold","label":"Long shot","p_open":1,"p_active":0.244,"p_room":0.28,"age_days":171,"expected_fill_days":52,"reasons":["conf:0","stale_co","velocity","ghost","win:tail","crowd:brand"],"computed_at":"2026-10-20T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/espace-soc-platform-engineer","json_url":"https://alion.io/job/espace-soc-platform-engineer.json","meta":{"generated_at":"2026-10-21T00:21:06Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":529,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":2438005},"rest":"https://alion.io/mcp/rest/get_company?id=2438005"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fespace-soc-platform-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fespace-soc-platform-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fespace-soc-platform-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/espace-soc-platform-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fespace-soc-platform-engineer"}]}