{"id":135218,"url":"https://alion.io/job/etched-advanced-packaging-sipi-engineer","title":"Advanced Packaging SI/PI Engineer","company":{"id":5021,"name":"Etched","domain":"etched.com","url":"https://alion.io/company/etched","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":90,"open_postings":79,"ghost_share":0.076,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":162,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":150000,"max":275000,"currency":"USD","period":"year","gross":null,"usd_annual":275000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys HFSS","optional":false},{"name":"Ansys SIwave","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"Keysight ADS","optional":false},{"name":"HPC","optional":true},{"name":"LLM","optional":true}],"status":"live","first_seen_at":"2026-08-27T16:53:09Z","employer_posted_date":"2026-08-27","last_verified_at":"2026-10-18T15:36:34Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":51},"description":"About Etched\nEtched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.\nJob Summary\nAs a Signal & Power Integrity Engineer you will be responsible for the electrical performance of our AI accelerator platform across silicon, package, and board. The ideal candidate will have extensive experience with high-power package and board designs, robust power delivery networks, and high-speed signaling solutions in advanced packaging. You will work closely with silicon, package, platform, and system teams to co-design world-class platforms with OSAT and ODM partners. Intense focus on pushing what is possible in power delivery and high-speed signaling for our silicon.\nKey Responsibilities\nSI/PI analysis of designs and optimization within 2D/2.5D/3D packages\n\nClose interaction with Package Layout Designers, ASIC PD and IP teams as well as Board Schematic/Layout/SI/PI teams to optimize the best electrical performance\n\nDrive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out.\n\nDrive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails.\n\nOwn ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams.\n\nSupport board-level SI/PI and rack-level scale-up topology studies, including rack test vehicle design and cable characterization.\n\nParticipating in cross-functional meetings and design reviews.\n\nYou may be a good fit if you have (Must-have qualifications)\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals.\n\n8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.\n\nProven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis.\n\nExperience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces.\n\nHands-on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS.\n\nExperience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs.\n\nTrack record of designing and correlating SI/PI test vehicles against silicon measurement during bring-up and lab characterization.\n\nStrong analytical and communication skills, comfortable presenting risk, sign-off status, and trade-offs to cross-functional leadership.\n\nDeeply creative and able to think from first principles.\n\nStrong candidates may also have experience with (Nice-to-have qualifications)\nFamiliarity with full RTL-to-GDSII context and how PD decisions interact with package and board PDN.\n\nExperience with multi-die, 2.5D, or 3D packaging signoff, including chip-package-system (CPS) co-design.\n\nProject management experience coordinating across internal teams, OSAT partners, and PCB ODMs.\n\nFamiliarity with modern ML and LLM model architectures, accelerator architectures, or HPC system design.\n\nStartup experience or comfort working in fast-paced environments.\n\nBenefits\nMedical, dental, and vision packages with generous premium coverage\n$500 per month credit for waiving medical benefits\n\nHousing subsidy of $2.5k per month for those living within walking distance of the office\n\nRelocation support for those moving to San Jose (Santana Row)\n\nVarious wellness benefits covering fitness, mental health, and more\n\nDaily lunch and dinner in our office\n\nUnlimited compute budget subject to ROI justification\n\nHow we’re different\nEtched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.\nWe are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.","description_format":"text","description_chars":4687,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":true,"industries":["Processors, MCUs & AI Chips","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-08-27T16:53:09Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 5","filings_12m":5,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":173500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":5}],"liveness":{"score":87,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.865,"p_room":1,"age_days":50,"expected_fill_days":162,"reasons":["conf:2","velocity","win:early"],"computed_at":"2026-10-17T05:46:00Z"},"pay":{"stated_usd_annual":275000,"is_top_pay":true},"html_url":"https://alion.io/job/etched-advanced-packaging-sipi-engineer","json_url":"https://alion.io/job/etched-advanced-packaging-sipi-engineer.json","meta":{"generated_at":"2026-10-18T16:34:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22189,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5021},"rest":"https://alion.io/mcp/rest/get_company?id=5021"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fetched-advanced-packaging-sipi-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fetched-advanced-packaging-sipi-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fetched-advanced-packaging-sipi-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/etched-advanced-packaging-sipi-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fetched-advanced-packaging-sipi-engineer"}]}