{"id":16820,"url":"https://alion.io/job/etched-dft-design-for-test-engineer","title":"DFT (Design For Test) Engineer","company":{"id":5021,"name":"Etched","domain":"etched.com","url":"https://alion.io/company/etched","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":90,"open_postings":79,"ghost_share":0.076,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":162,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":150000,"max":275000,"currency":"USD","period":"year","gross":null,"usd_annual":275000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Tessent","optional":false}],"status":"live","first_seen_at":"2026-02-28T00:41:40Z","employer_posted_date":"2026-02-28","last_verified_at":"2026-10-18T08:47:06Z","board_verified":true,"closed_at":null,"days_open":232,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":232},"description":"About Etched\nEtched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.\nJob Summary\nWe are seeking a highly skilled and motivated Design For Testability (DFT) Engineer to join our dynamic team. The ideal candidate will be responsible for ensuring the robust testability of integrated circuits (ICs) from the design phase through to production. This role is crucial in improving the efficiency and effectiveness of our testing processes, thereby enhancing overall product quality.\nKey responsibilities\nDevelop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation.\n\nIntegrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST).\n\nCollaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle.\n\nAnalyze test results and silicon debug data to provide design feedback and drive improvements in coverage, yield, and reliability.\n\nCreate and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features.\n\nApply simulation-based and formal verification techniques to ensure high confidence in DFT logic correctness.\n\nConduct internal DFT audits and design reviews to proactively identify and resolve gaps in testability or coverage.\n\nSupport silicon bring-up, debug, and failure analysis during post-silicon validation to ensure successful product launch.\n\nPartner with test engineering teams to develop and optimize Automated Test Equipment (ATE) programs for volume production.\n\nGenerate production-quality test patterns and ensure robust failure analysis capability in high-volume environments.\n\nCollaborate with manufacturing and quality teams to implement data-driven test process improvements and monitor long-term product health.\n\nEnsure test strategies are aligned with product milestones, manufacturing timelines, and quality/reliability targets.\n\nAuthor and maintain detailed documentation for DFT architecture, test plans, procedures, and debug guides.\n\nShare best practices through training sessions, onboarding, and mentorship to enhance DFT awareness across design and test teams.\n\nStay current with emerging DFT technologies, industry trends, and evolving standards to continually improve internal methodologies.\n\nYou may be a good fit if you have\n10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products.\n\nA deep understanding of digital design, verification methodologies, and DFT implementation practices.\n\nProficiency in System Verilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).\n\nScripting and automation experience using Python, Perl, or TCL to streamline DFT implementation and test processes.\n\nTrack record of leading DFT initiatives across multiple product generations in high-performance or high-volume silicon environments.\n\nStrong analytical and debugging skills, with the ability to work across teams to resolve complex testability issues.\n\nExcellent communication and collaboration abilities, with a focus on clarity and cross-functional alignment.\n\nA Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred).\n\nStrong candidates may also have experience with\nMixed-signal DFT methodologies and integration of analog testability into SoC workflows.\n\nIndustry standards such as IEEE 1149.1 (JTAG), IEEE 1500, and experience applying them in complex designs.\n\nYield analysis, product engineering, and contributions to test cost reduction and quality improvement programs.\n\nBenefits\nMedical, dental, and vision packages with generous premium coverage\n$500 per month credit for waiving medical benefits\n\nHousing subsidy of $2.5k per month for those living within walking distance of the office\n\nRelocation support for those moving to San Jose (Santana Row)\n\nVarious wellness benefits covering fitness, mental health, and more\n\nDaily lunch + dinner in our office\n\nUnlimited compute budget subject to ROI justification\n\nHow we’re different\nEtched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.\nWe are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.","description_format":"text","description_chars":5074,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":true,"industries":["Processors, MCUs & AI Chips","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-02-28T00:41:40Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 5","filings_12m":5,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":173500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":5}],"liveness":{"score":32,"band":"fade","label":"Fading","p_open":1,"p_active":0.732,"p_room":0.44,"age_days":231,"expected_fill_days":162,"reasons":["conf:2","velocity","win:tail","crowd:"],"computed_at":"2026-10-17T05:46:00Z"},"pay":{"stated_usd_annual":275000,"is_top_pay":true},"html_url":"https://alion.io/job/etched-dft-design-for-test-engineer","json_url":"https://alion.io/job/etched-dft-design-for-test-engineer.json","meta":{"generated_at":"2026-10-18T09:11:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13682,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5021},"rest":"https://alion.io/mcp/rest/get_company?id=5021"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fetched-dft-design-for-test-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fetched-dft-design-for-test-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fetched-dft-design-for-test-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/etched-dft-design-for-test-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fetched-dft-design-for-test-engineer"}]}