{"id":180987,"url":"https://alion.io/job/etched-physical-design-engineer-full-chip-implementation","title":"Physical Design Engineer - Full Chip Implementation","company":{"id":5021,"name":"Etched","domain":"etched.com","url":"https://alion.io/company/etched","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":90,"open_postings":79,"ghost_share":0.076,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":162,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":200000,"max":300000,"currency":"USD","period":"year","gross":null,"usd_annual":300000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Cadence Pegasus","optional":false},{"name":"Cadence Tempus","optional":false},{"name":"LLM","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-07-23T03:30:06Z","employer_posted_date":"2026-07-23","last_verified_at":"2026-10-16T19:08:59Z","board_verified":true,"closed_at":null,"days_open":85,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":85},"description":"About Etched\nEtched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.\nJob Summary\nEtched is building a new category of AI hardware: frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation-encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs-from synthesis through to GDSII completion. You will lead critical efforts in these areas, leveraging our PD flows to drive aggressive PPA optimization and timing closure. You will collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.\nKey Responsibilities\nOwn full-chip clocking across all PVT corners and modes.\n\nManage MMMC (Multi-Mode Multi-Corner) timing closure at the top level.\n\nOwn timing constraints and hierarchical timing budgeting between top level and blocks.\n\nDrive functional and timing ECO closure and achieve final timing signoff for tapeout.\n\nOwn end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration.\n\nDebug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus.\n\nBuild a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.\n\nYou may be a good fit if you have\n10+ years of previous experience with chip planning, top level PD, floorplanning\n\nExperience with top-level and full-chip closure on advanced process nodes (5nm and below)\n\nExperience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows\n\nExperience with Synopsys PrimeTime and Cadence Tempus for timing signoff\n\nExperience with Pegasus or Calibre for physical verification signoff\n\nExperience with hierarchical timing budgeting, constraint management, and ECO closure\n\nExperience with Cadence Innovus for top-level assembly, routing, and layout fixes\n\nDeeply creative and able to think from first principles\n\nStrong candidates may also have experience with\nFamiliarity with modern ML and LLM model architectures\n\nAbility to program with Python or another scripting language\n\nFamiliarity with AI tools for programming/coding\n\nStartup experience or comfort working in fast-paced environments\n\nBenefits\nMedical, dental, and vision packages with generous premium coverage\n$500 per month credit for waiving medical benefits\n\nHousing subsidy of $2.5k per month for those living within walking distance of the office\n\nRelocation support for those moving to San Jose (Santana Row)\n\nVarious wellness benefits covering fitness, mental health, and more\n\nDaily lunch and dinner in our office\n\nUnlimited compute budget subject to ROI justification\n\nHow we’re different\nEtched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.\nWe are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.","description_format":"text","description_chars":3682,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":true,"industries":["Processors, MCUs & AI Chips","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-08-31T18:37:59Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 5","filings_12m":5,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":173500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":5}],"liveness":{"score":74,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.826,"p_room":0.9,"age_days":85,"expected_fill_days":162,"reasons":["conf:0","win:mid"],"computed_at":"2026-10-16T05:45:00Z"},"pay":{"stated_usd_annual":300000,"is_top_pay":true},"html_url":"https://alion.io/job/etched-physical-design-engineer-full-chip-implementation","json_url":"https://alion.io/job/etched-physical-design-engineer-full-chip-implementation.json","meta":{"generated_at":"2026-10-16T19:09:51Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4688,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-17T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5021},"rest":"https://alion.io/mcp/rest/get_company?id=5021"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fetched-physical-design-engineer-full-chip-implementation"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fetched-physical-design-engineer-full-chip-implementation"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fetched-physical-design-engineer-full-chip-implementation"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/etched-physical-design-engineer-full-chip-implementation\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fetched-physical-design-engineer-full-chip-implementation"}]}