{"id":995580,"url":"https://alion.io/job/etched-substrate-ic-package-layout-design-engineer","title":"Substrate IC Package Layout Design Engineer","company":{"id":5021,"name":"Etched","domain":"etched.com","url":"https://alion.io/company/etched","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":87,"open_postings":78,"ghost_share":0.128,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":142,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Taipei, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":46000,"max_usd":98000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Allegro","optional":false}],"status":"live","first_seen_at":"2026-09-17T06:50:41Z","employer_posted_date":"2026-09-17","last_verified_at":"2026-11-07T12:26:50Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":50},"description":"About Etched\nEtched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by billions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.\nJob Summary\nAs a Substrate IC Package Layout Design Engineer you will be responsible for the end-to-end design of complex IC substrate packages, supporting high-power consumption and high-speed signaling. The ideal candidate will have extensive experience with large substrate designs (>50mm), complex power delivery networks, and high-speed signaling solutions (up to and beyond 50GHz). You will work closely with silicon, signal integrity, power integrity, and system help co-design world class substates with OSAT providers. Intense focus on optimization for power delivery through substrate, pushing what’s possible.\nKey responsibilities\nIC Substrate Layout Design\n\nLead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.\n\nDesign large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements.\n\nEnsure robust power delivery designs capable of supporting >700W custom silicon solutions.\n\nHigh-Speed Signal Routing & Integrity\n\nDevelop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk.\n\nCollaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout.\n\nAdvanced Packaging & CoWoS Integration\n\nOptimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance.\n\nWork closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability.\n\nDesign Validation & Verification\n\nPerform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs.\n\nDevelop and maintain design documentation and guidelines for future substrate designs.\n\nSupport design reviews and provide technical guidance to junior team members.\n\nYou may be a good fit if you have\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\n\n10+ years of experience in IC substrate layout design for high-performance processors or accelerators.\n\nExtensive experience with large substrate packages (>50mm) and complex high-density layouts.\n\nProven experience with high-power (700W+) package designs and robust power delivery networks.\n\nExpertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches).\n\nStrong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWos.\n\nAdvanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification).\n\nDeep understanding of SI/PI principles and how they apply to package-level design.\n\nStrong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment.\n\nBenefits\nCompetitive compensation packages, including generous equity packages\n\nComprehensive insurance coverage and other top-of-market benefits\n\nHow we’re different\nEtched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.\nWe are a fully in-person team in San Jose and Taipei, and greatly value engineering skills. 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