{"id":1251996,"url":"https://alion.io/job/exiger-technologies-senior-soc-design-engineer","title":"Senior SoC Design Engineer","company":{"id":3806605,"name":"Exiger Technologies","domain":"exiger.co.in","url":"https://alion.io/company/exiger-technologies","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":48000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-16T06:02:10Z","employer_posted_date":null,"last_verified_at":"2026-09-16T06:02:10Z","board_verified":false,"closed_at":null,"days_open":32,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":32},"description":"Job Description :\n\nWe are hiring an experienced Senior SoC Design Engineer / SoC Expert (RTL-to-GDSII) for a leading semiconductor client based in Bangalore.\n\nWe are seeking a highly experienced SoC Expert with 10+ years of experience in ASIC/SoC development and proven expertise across the complete RTL-to-GDSII design flow. The candidate will be responsible for leading the architecture, design, implementation, integration, verification, and physical realization of complex SoCs from specification through tape-out and silicon bring-up.\n\nThe ideal candidate should possess deep technical knowledge of digital design, SoC integration, synthesis, STA, low-power methodologies, DFT, physical design, and signoff flows while collaborating across cross-functional teams.\n\nKey Responsibilities : \n\nSoC Architecture & Design :\n\n- Define and review SoC architecture, micro-architecture, and design specifications.\n\n- Drive RTL development using Verilog/SystemVerilog for NVM memory.\n\n- Perform IP integration and top-level SoC assembly.\n\n- Develop scalable and reusable design methodologies.\n\nRTL Development & Verification :\n\n- Lead RTL coding, lint, CDC, RDC, and quality checks.\n\n- Collaborate with verification teams on test plans, coverage closure, and regression signoff.\n\n- Debug functional issues and drive root-cause analysis.\n\n- Ensure compliance with coding guidelines and design best practices.\n\nSynthesis & Design Implementation :\n\n- Own RTL-to-Gate synthesis flow and timing closure activities.\n\n- Develop and maintain synthesis constraints (SDC).\n\n- Drive area, power, and performance optimizations.\n\n- Support ECO implementation and netlist signoff activities.\n\nPhysical Design & Signoff :\n\n- Work closely with Physical Design teams through floorplanning, placement, CTS, routing, and optimization.\n\n- Perform timing analysis and closure across multiple PVT corners.\n\n- Support power integrity, IR drop, EM analysis, and low-power signoff.\n\n- Analyze and resolve DRC, LVS, and physical verification issues.\n\n- Drive GDSII release readiness and tape-out signoff.\n\nDFT & Testability :\n\n- Define and review DFT architecture including Scan, MBIST, LBIST, and JTAG.\n\n- Support ATPG pattern generation and coverage closure.\n\n- Collaborate with product engineering and validation teams during silicon bring-up.\n\nPost-Silicon Support :\n\n- Support first silicon debug and characterization.\n\n- Analyze silicon failures and implement corrective actions.\n\n- Work with system, validation, and customer teams to resolve issues.\n\nTechnical Leadership :\n\n- Mentor junior engineers and provide technical guidance.\n\n- Drive design reviews and signoff meetings.\n\n- Contribute to methodology improvements and automation initiatives.\n\n- Interface with customers, external partners, and executive stakeholders when required.\n\nRequired Qualifications :\n\n- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.\n\n- 10+ years of experience in ASIC/SoC design and development.\n\n- Proven experience in complete RTL-to-GDSII implementation flow.\n\nMandatory Skills :\n\n- RTL-to-GDSII Flow\n\n- Verilog/SystemVerilog\n\n- SoC Integration\n\n- Synthesis\n\n- Static Timing Analysis (STA)\n\n- Clock Domain Crossing (CDC)\n\n- Low-Power Design Methodologies (UPF/CPF)\n\n- Physical Design Concepts\n\n- DFT (Scan, MBIST, LBIST, JTAG, ATPG)\n\n- Silicon Debug & Bring-up\nSkills\nVerilog, System Verilog, Static Timing Analysis, DFT, Synthesis, Clock Domain Crossing, Physical Design, SoC, RTL, GDS","description_format":"text","description_chars":3522,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response"],"lifecycle":[{"event":"open","at":"2026-09-25T18:04:06Z"}],"visa":[],"liveness":{"score":24,"band":"cold","label":"Long shot","p_open":0.6,"p_active":0.729,"p_room":0.55,"age_days":30,"expected_fill_days":26,"reasons":["seen:30","velocity","win:tail"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/exiger-technologies-senior-soc-design-engineer","json_url":"https://alion.io/job/exiger-technologies-senior-soc-design-engineer.json","meta":{"generated_at":"2026-10-18T13:21:15Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":19856,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3806605},"rest":"https://alion.io/mcp/rest/get_company?id=3806605"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fexiger-technologies-senior-soc-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fexiger-technologies-senior-soc-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fexiger-technologies-senior-soc-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/exiger-technologies-senior-soc-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fexiger-technologies-senior-soc-design-engineer"}]}