First seen by Alion on Feb 13, 2026.
Responsibilities Design and implement RTL for components of a neural network accelerator Translate architectural specifications into efficient, maintainable hardware implementations Collaborate with hardware architects and verification engineers to ensure functional correctness and performance targets Write tests, assertions, or simple verification environments to validate your designs Contribute to improving internal hardware design and verification workflows using scripting and automation Participate in design reviews, debugging, and bring-up of new hardware blocks
Requirements The candidate must have: Proficiency in HDL languages like SystemVerilog and/or VHDL Strong foundation in digital design, computer architecture, and VLSI through coursework or projects Familiarity with ASIC or FPGA design flows Proficiency in Python for scripting and automation Strong technical communication skills and ability to collaborate across disciplines BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field The ideal candidate will also have: Experience or coursework involving RTL design and microarchitecture Proficiency with UVM design verification frameworks Knowledge of physical design and verification Experience or coursework related to on-chip interconnects Interest in or exposure to machine learning accelerators Benefits 401(k) Medical insurance Vision insurance Dental insurance Commuter benefits Disability insurance Paid maternity leave Paid paternity leave Child care support femtoAI is an equal opportunity employer committed to a diverse workforce which strives to create an inclusive working environment empowering everyone to do their best work. We do not discriminate on the basis of race, ethnicity, religion, gender, gender identity, sexual orientation, age, marital status, veteran status, or disability status.

