{"id":2916423,"url":"https://alion.io/job/femtosense-senior-ml-compiler-engineer","title":"Senior ML Compiler Engineer","company":{"id":3784215,"name":"FEMTOSENSE","domain":"femto.ai","url":"https://alion.io/company/femto-2","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Zoho Recruit","truth_index":{"grade":"B","score":75,"open_postings":5,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-23T05:54:15Z"}},"role":"AI/ML","role_family":"AI/ML","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Bruno, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":147000,"max_usd":283000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1268},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Apache TVM","optional":false},{"name":"MLIR","optional":false},{"name":"XLA","optional":false}],"status":"live","first_seen_at":"2026-04-15T00:00:00Z","employer_posted_date":"2026-04-15","last_verified_at":"2026-10-23T09:18:18Z","board_verified":true,"closed_at":null,"days_open":191,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":191},"description":"You will design and build core components of our ML compiler, owning critical parts of the transformation and optimization pipeline.\nYour work will directly determine whether models fit within hardware constraints and achieve real-time performance.\nWhat You’ll Do\nDesign and implement compiler architecture across:\nIR design and transformation pipelines\nOptimization strategies for scheduling, tiling, and memory reuse\nLead development of complex compiler passes such as:\nGlobal memory allocation and liveness-driven reuse\nCross-operator fusion and graph partitioning\nHardware-aware scheduling strategies\nDevelop cost models and optimization heuristics\nExplore advanced techniques:\nConstraint-based optimization (e.g., ILP/MILP/CP)\nScheduling optimization\nDrive debugging of system-level issues (correctness, performance, HW mismatches)\nCollaborate with hardware teams on co-design of abstractions and execution models\nRequirements\nRequired qualifications and experience:\n4+ years of experience in compilers, systems, or performance engineering\nMasters or PhD in Computer Science, Electrical Engineering, Math, or a related field\nDeep experience with at least one:\nML compiler frameworks (MLIR, TVM, XLA, etc.)\nLow-level optimization (scheduling, memory, tiling)\nProven ability to design non-trivial compiler systems or passes\nStrong intuition for performance across compute, memory, and data movement\nComfort working with hardware constraints\nNice to have:\nExperience with constraint solvers (MILP, ILP, CP)\nBackground in accelerator architectures or embedded systems\nExperience optimizing ML workloads for latency/power\nFamiliarity with DSP or real-time signal processing\nBenefits\n401(k)\nMedical insurance\nVision insurance\nDental insurance\nCommuter benefits\nDisability insurance\nPaid maternity leave\nPaid paternity leave\nChild care support\nfemtoAI is an equal opportunity employer committed to a diverse workforce which strives to create an inclusive working environment empowering everyone to do their best work. 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