{"id":1973101,"url":"https://alion.io/job/fortaegis-design-verification-engineer","title":"Design Verification Engineer","company":{"id":3880577,"name":"Fortaegis","domain":"fortaegis.com","url":"https://alion.io/company/fortaegis","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Teamtailor","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Amsterdam, Netherlands"],"countries":["NL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":69000,"max_usd":129000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":17},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-08-17T08:42:03Z","employer_posted_date":"2026-08-17","last_verified_at":"2026-10-18T15:29:16Z","board_verified":true,"closed_at":null,"days_open":62,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":62},"description":"Job description\nFortaegis is a fast-scaling, highly ambitious and cutting-edge semiconductor company. We are looking for a Design Verification Engineer responsible for verifying RTL designs for FPGA and ASIC-based products. The role focuses on ensuring that system-level and block-level requirements are correctly implemented in hardware designs and identifying functional issues early. We are looking for candidates with not only an exceptional skillset, but also an exceptional mindset, willing to go above and beyond to make our hardware engineering team even better.\nJob requirements\n5+ years of experience in RTL functional verification for FPGA and/or ASIC designs\n\nAdvanced knowledge of SystemVerilog and UVM\n\nHands-on experience with verification EDA tools (e.g., Siemens, Cadence, Synopsys)\n\nStrong analytical and problem-solving abilities with keen attention to detail\n\nExperience with formal verification techniques is a plus\n\nHigh-speed networking (Ethernet, PCIe) or cryptographic IP experience is advantageous\n\nEffective communication, teamwork skills and ability to collaborate across functions\n\nAbility to take ownership and solve problems beyond the scope of the job description, with a flexible, solution-oriented mindset\n\nJob responsibilities\nDevelop and execute verification strategies for intricate FPGA and ASIC RTL designs\n\nDesign, implement, and maintain verification environments, including automated test suites and infrastructure, following industry-standard methodologies\n\nIdentify, debug, and document design issues, collaborating closely with design engineers to validate functionality and performance\n\nImplement coverage-focused verification approaches to achieve thorough verification of all design features\n\nCoordinate with design, architecture, and software teams to ensure smooth integration and verification of designs\n\nStay up-to-date with verification tools, methodologies, and best practices\n\nAdditional information\nThe successful candidate will have the unique opportunity to participate in shaping the future of our visionary company, contributing to the development of ultra-secure and high-performance products. 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