{"id":3514386,"url":"https://alion.io/job/fortaegis-digital-design-engineer","title":"Digital Design Engineer","company":{"id":3880577,"name":"Fortaegis","domain":"fortaegis.com","url":"https://alion.io/company/fortaegis","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Teamtailor","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Amsterdam, Netherlands"],"countries":["NL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":67000,"max_usd":119000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":23},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cocotb","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-10-02T11:02:16Z","employer_posted_date":"2026-10-02","last_verified_at":"2026-10-30T14:45:03Z","board_verified":true,"closed_at":null,"days_open":28,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":28},"description":"Job description\nFortaegis is a fast-scaling, highly ambitious and cutting-edge semiconductor company. We are looking for a Digital Design Engineer responsible for architecting, developing, and integrating RTL and IP for FPGA and ASIC-based products. The role focuses on turning system-level requirements into high-quality, reusable digital designs, ensuring they are correctly implemented, meet performance goals, and integrate smoothly across the system. We are looking for candidates with not only an exceptional skillset, but also an exceptional mindset, willing to go above and beyond to make our hardware engineering team even better.\nJob requirements\n5+ years of experience in digital design and RTL development for FPGA and/or ASIC, with advanced knowledge of SystemVerilog and/or Verilog (VHDL a plus)\nProven experience developing and integrating IP in complex SoC or FPGA-based systems, including standard interfaces (e.g., AXI/AXI-Stream, PCIe, Ethernet, DDR, SerDes)\nHands-on experience with synthesis and implementation EDA tools (e.g., Vivado, Synopsys, Cadence) and strong understanding of static timing analysis, CDC, and low-power techniques\nWorking knowledge of verification methodologies and simulators (e.g., UVM, cocotb, SVA; Siemens, Cadence, Synopsys) and scripting for automation (Python, Tcl, Perl)\nStrong analytical and problem-solving abilities with keen attention to detail, and the ability to translate system requirements into reusable RTL and IP while weighing trade-offs among performance, area, power, and schedule\nHigh-speed networking (Ethernet, PCIe) or cryptographic IP experience is advantageous\nExperience with IP evaluation or vendor engagement is a plus\nEffective communication, teamwork skills, and ability to collaborate across functions\nAbility to take ownership and solve problems beyond the scope of the job description, with a flexible, solution-oriented mindset\nJob responsibilities\nDesign and implement RTL (SystemVerilog/Verilog, VHDL) based on system-level requirements, including microarchitecture documents, block diagrams, and interface specifications\nDevelop, integrate, and maintain custom and third-party IP (e.g., networking, memory controllers, PCIe, high-speed SerDes), and evaluate IP for functionality, performance, area/resource usage, and integration risk\nIntegrate IP and subsystems at the block and top level, including bus fabrics (e.g., AXI), clocking, reset, and CDC strategy\nRun synthesis and implementation flows (FPGA or ASIC), develop timing constraints (SDC/XDC), and drive timing closure, area, and power optimization\nPerform RTL quality checks (lint, CDC/RDC) and support verification through unit-level testbenches, assertions, and failure debug, as well as simulation, emulation, and hardware bring-up\nCoordinate with verification, architecture, hardware, software, and firmware teams on register maps, integration requirements, and design reviews to ensure smooth integration of designs\nStay up-to-date with design tools, methodologies, and best practices, and contribute to architecture and flow improvements\nAdditional information\nThe successful candidate will have the unique opportunity to participate in shaping the future of our visionary company, contributing to the development of ultra-secure and high-performance products. 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