{"id":141738,"url":"https://alion.io/job/fractile-seniorprincipal-physical-design-engineer","title":"Senior/Principal Physical Design Engineer","company":{"id":51523,"name":"Fractile","domain":"fractile.ai","url":"https://alion.io/company/fractile","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":95,"open_postings":36,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":231,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["London, United Kingdom","Bristol, United Kingdom"],"countries":["GB"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":95000,"max_usd":171000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":23},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Formal Verification","optional":true},{"name":"HPC","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-01-02T13:34:33Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T05:58:56Z","board_verified":true,"closed_at":null,"days_open":292,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":292},"description":"Senior / Principal Physical Design Engineer\nAbout Fractile\nFractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.\nThe workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.\nWe are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next-generation chip designs. As a Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off, including opportunities for full-chip ownership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.\nKey Responsibilities:\nDrive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.\nWork on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.\nPerform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.\nEnsure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.\nCollaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.\nDevelop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.\nInterface with foundries and process engineers to ensure manufacturability and yield optimisation.\nWork closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.\nWork with advanced AI tools and models to improve productivity, analysis, and design quality.\nPreferred Qualifications:\nBachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.\n8+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).\nStrong proficiency in EDA tools for place & route, STA, and sign-off.\nSolid understanding of CMOS technology, semiconductor physics, and process limitations.\nExperience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.\nExpertise in timing closure, signal integrity, IR drop analysis, and formal verification.\nProficiency in scripting languages like TCL, Perl, or Python for automation.\nExcellent problem-solving skills, communication, and teamwork in a collaborative design environment.\nExperience in high-performance computing (HPC), AI accelerators, or networking chips.\nExperience or strong interest in leveraging advanced AI tools and models within engineering workflow\nWhat We Offer\nCompetitive salary: A competitive salary reflective of your experience and the specialist nature of the role\nEquity & Ownership: meaningful equity so everyone shares in the value creation.\n\nBenefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.\n\nDiverse & fun office: we believe the hardest problems get solved by the broadest range of minds. We are committed to Equal Employment Opportunity through attracting and retaining a diverse team and building an inclusive environment.\nFractile is seeking to increase the clock speed of global progress, one chip at a time. We’ve recently raised $220M from investors including Founders Fund and Accel and our most important work lies ahead. Join us!\nExport controls\nOur work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.","description_format":"text","description_chars":4803,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-01-02T13:34:33Z"}],"visa":[{"country":"GB","licensed_sponsor":true,"evidence":"Licensed UK visa sponsor (Skilled Worker)","filings_12m":null,"filings_prev_12m":null,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Skilled Worker","cap_exempt":false,"checked_at":"2026-10-22T06:27:10+00:00","sources":["UK Home Office: register of licensed sponsors (workers)"],"filings_for_role_12m":0}],"liveness":{"score":27,"band":"fade","label":"Fading","p_open":1,"p_active":0.619,"p_room":0.44,"age_days":292,"expected_fill_days":231,"reasons":["conf:0","win:tail","crowd:"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/fractile-seniorprincipal-physical-design-engineer","json_url":"https://alion.io/job/fractile-seniorprincipal-physical-design-engineer.json","meta":{"generated_at":"2026-10-22T08:07:57Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4174,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":51523},"rest":"https://alion.io/mcp/rest/get_company?id=51523"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Ffractile-seniorprincipal-physical-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Ffractile-seniorprincipal-physical-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Ffractile-seniorprincipal-physical-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/fractile-seniorprincipal-physical-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Ffractile-seniorprincipal-physical-design-engineer"}]}