{"id":1403684,"url":"https://alion.io/job/general-dynamics-mission-systems-advanced-asic-fpga-design-engineer","title":"Advanced ASIC FPGA Design Engineer","company":{"id":1836162,"name":"General Dynamics Mission Systems","domain":"gdmissionsystems.com","url":"https://alion.io/company/gdmissionsystems-com","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"iCIMS","truth_index":{"grade":"A","score":100,"open_postings":4,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":13,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Scottsdale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":94000,"max_usd":173000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1517},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agile","optional":false},{"name":"CI/CD","optional":false},{"name":"Siemens ModelSim","optional":false},{"name":"Siemens QuestaSim","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"GitLab","optional":true},{"name":"GitLab CI","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-28T16:58:28Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-31T05:59:41Z","board_verified":true,"closed_at":null,"days_open":32,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":32},"description":"Basic Qualifications\nBachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.\nCLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.\nResponsibilities for this Position\nWhat You'll Do\nArchitect and implement high-performance FPGA designs in VHDL and/or Verilog targeting Xilinx and Microchip device families.\nPerform synthesis, place-and-route, and timing closure using Vivado or Libero, including advanced techniques such as pipelining, register retiming, floorplanning, and physical optimization\nDevelop and execute block-level simulations using QuestaSim/ModelSim with code coverage analysis (statement, branch, condition, expression)\nCreate self-checking testbenches for correctness verification\nDesign high-speed interfaces for inter-module communication and system integration\nCollaborate with systems engineers, software developers, and verification engineers in an Agile development environment\nParticipate in design reviews, peer code reviews, and documentation of design specifications and interface control documents\nContribute to CI/CD pipeline development for automated synthesis, simulation regression, and coverage tracking\nSupport integration and lab bring-up activities, including on-target FPGA debug using ILAs and JTAG-based tools\nRequired Qualifications\nStrong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design\nHands-on experience with Xilinx Vivado Design Suite or Microchip Libero for synthesis, implementation, and timing analysis\nExperience targeting Xilinx and Microchip device families\nAbility to achieve timing closure on designs at 300+ MHz clock rates\nExperience with FPGA simulation tools (QuestaSim or ModelSim)\nProficiency in writing self-checking testbenches with automated pass/fail determination\nUnderstanding of high-speed digital design principles: pipelining, clock domain crossing (CDC), metastability mitigation, and synchronous design\nExperience with AXI-Stream, AXI4, or similar on-chip bus protocols\nAbility to read and interpret timing reports, utilization summaries, and critical-path analysis output\nStrong written and verbal communication skills for design documentation and technical presentations\nS. Citizenship and ability to obtain/maintain a Secret security clearance\nPreferred Qualifications\nExperience with cryptographic algorithm implementation in hardware (AES, GCM, SHA, ECC, RSA, or similar)\nExperience with high-speed serial interfaces: PCIe, Ethernet (10G/25G/100G), Fibre Channel, Aurora, or GTY/GTM transceivers\nExperience with CI/CD pipelines for FPGA development (GitLab CI) including automated synthesis and regression testing\nProficiency in scripting languages (Tcl, Python, Bash) for build automation and design flow scripting\nExperience with version control systems (GitLab) and collaborative development workflows\nExperience with Xilinx IP cores: FIFO Generator, Clock Wizard, MIG/DDR controllers, DMA/Bridge subsystems\nExperience with embedded processors in FPGA (MicroBlaze, Zynq PS, Versal AI Engine)\nSalary Note\nThis estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.Combined Salary Range\nUSD $135,396.00 - USD $150,205.00 /Yr.Company Overview\nGeneral Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!\nEqual Opportunity Employer / Individuals with Disabilities / Protected Veterans","description_format":"text","description_chars":4637,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[]},"benefits":["Flexible schedule"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Military","National Security","Defense Manufacturing"],"lifecycle":[{"event":"open","at":"2026-09-28T16:58:28Z"}],"visa":[],"liveness":{"score":13,"band":"cold","label":"Long shot","p_open":0.6,"p_active":0.599,"p_room":0.35,"age_days":32,"expected_fill_days":13,"reasons":["seen:32","velocity","win:tail","comp:brand"],"computed_at":"2026-10-31T05:58:55Z"},"pay":null,"html_url":"https://alion.io/job/general-dynamics-mission-systems-advanced-asic-fpga-design-engineer","json_url":"https://alion.io/job/general-dynamics-mission-systems-advanced-asic-fpga-design-engineer.json","meta":{"generated_at":"2026-10-31T06:18:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":9238,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-01T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1836162},"rest":"https://alion.io/mcp/rest/get_company?id=1836162"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fgeneral-dynamics-mission-systems-advanced-asic-fpga-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fgeneral-dynamics-mission-systems-advanced-asic-fpga-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fgeneral-dynamics-mission-systems-advanced-asic-fpga-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/general-dynamics-mission-systems-advanced-asic-fpga-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fgeneral-dynamics-mission-systems-advanced-asic-fpga-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":1403684}},{"tool":"search_jobs","arguments":{"company":"gdmissionsystems.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":1403684},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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