{"id":3301587,"url":"https://alion.io/job/general-dynamics-mission-systems-advanced-asic-fpga-verification-engineer","title":"Advanced ASIC FPGA Verification Engineer","company":{"id":1836162,"name":"General Dynamics Mission Systems","domain":"gdmissionsystems.com","url":"https://alion.io/company/gdmissionsystems-com","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"iCIMS","truth_index":{"grade":"A","score":100,"open_postings":4,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":11,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Scottsdale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":135396,"max":150205,"currency":"USD","period":"year","gross":null,"usd_annual":150205},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"CI/CD","optional":false},{"name":"Formal Verification","optional":false},{"name":"GitLab CI","optional":false},{"name":"Jenkins","optional":false},{"name":"Siemens ModelSim","optional":false},{"name":"Siemens QuestaSim","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"Git","optional":true},{"name":"GitHub Actions","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-26T23:50:15Z","employer_posted_date":"2026-10-26","last_verified_at":"2026-10-28T08:22:24Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Basic Qualifications\nBachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.\nCLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.\nResponsibilities for this Position\nWhat You'll Do\nTake ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level integration testbenches\nCreate comprehensive verification plans with functional coverage models, coverage goals, and closure criteria aligned to design specifications\nImplement constrained-random stimulus generators, monitors, scoreboards, and functional coverage collectors using SystemVerilog, VHDL and UVM\nDrive code coverage (statement, branch, condition, expression, toggle) and functional coverage to closure, analyzing coverage holes and developing targeted stimulus to fill gaps\nDevelop and maintain automated simulation regression suites that run across multiple test configurations and random seeds\nBuild and improve CI/CD pipelines for automated verification workflows -- including nightly regression runs, coverage trend tracking, and automated results reporting using Jenkins, GitLab CI, or similar platforms\nPerform assertion-based verification (ABV) using SystemVerilog Assertions (SVA) to capture protocol rules, interface contracts, and design invariants\nDebug complex design issues using waveform analysis (QuestaSim, Vivado), assertion failures, and coverage-driven investigation\nCollaborate closely with FPGA design engineers during architecture definition to ensure designs are verification-friendly and observable\nReview and contribute to design specifications, interface control documents, and verification closure reports\nMentor junior verification engineers on UVM methodology, coverage-driven verification practices, and debugging techniques\nSupport formal verification activities including property checking, connectivity verification, and equivalence checking where applicable\nRequired Qualifications\nStrong proficiency in SystemVerilog for verification, VHDL for verification including constrained-random stimulus, functional coverage, and assertions\nHands-on experience with UVM (Universal Verification Methodology) including environment architecture, component development, and sequence libraries\nExperience with industry-standard simulation tools: QuestaSim/ModelSim Simulators\nDemonstrated ability to develop verification plans, define coverage models, and drive coverage to closure\nExperience with code coverage metrics (statement, branch, condition, expression, toggle) and coverage analysis workflows\nProficiency in VHDL and/or Verilog for reading and understanding design RTL\nExperience with waveform debugging and signal-level analysis\nUnderstanding of AXI-Stream, AXI4, and similar on-chip bus protocols from a verification perspective\nKnowledge of clock domain crossing (CDC) verification concepts and metastability analysis\nStrong written and verbal communication skills for verification plans, coverage reports, and technical presentations\nS. Citizenship and ability to obtain/maintain a Secret security clearance\nPreferred Qualifications\nExperience verifying cryptographic hardware implementations (AES, GCM, SHA, ECC, RSA, or similar)\nExperience with CI/CD pipeline development and maintenance for FPGA verification (GitLab CI, GitHub Actions) -- including automated regression management, seed management, and coverage merging\nProficiency in scripting languages (Python, Tcl, Bash, Perl) for verification automation, log parsing, and results analysis\nExperience with Xilinx Vivado Design Suite and FPGA-specific verification challenges (timing simulation, post-synthesis/post-route verification)\nKnowledge of CDC analysis tools (Questa CDC) and lint/design rule checking tools\nExperience with emulation or prototyping platforms for hardware-in-the-loop verification\nKnowledge of AXI protocol specification and Questa verification IP (QVIP) usage for protocol compliance checking\nExperience with version control (Git), code review processes, and collaborative development workflows\nSalary Note\nThis estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.Combined Salary Range\nUSD $135,396.00 - USD $150,205.00 /Yr.Company Overview\nGeneral Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!\nEqual Opportunity Employer / Individuals with Disabilities / Protected Veterans","description_format":"text","description_chars":5738,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[]},"benefits":["Flexible schedule"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Military","C4ISR","Defense Manufacturing"],"lifecycle":[{"event":"open","at":"2026-10-26T23:50:15Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":11,"reasons":["conf:2","velocity","win:early","comp:brand"],"computed_at":"2026-10-28T05:59:10Z"},"pay":{"stated_usd_annual":150205,"is_top_pay":false},"html_url":"https://alion.io/job/general-dynamics-mission-systems-advanced-asic-fpga-verification-engineer","json_url":"https://alion.io/job/general-dynamics-mission-systems-advanced-asic-fpga-verification-engineer.json","meta":{"generated_at":"2026-10-28T09:17:19Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12069,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1836162},"rest":"https://alion.io/mcp/rest/get_company?id=1836162"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fgeneral-dynamics-mission-systems-advanced-asic-fpga-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fgeneral-dynamics-mission-systems-advanced-asic-fpga-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fgeneral-dynamics-mission-systems-advanced-asic-fpga-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/general-dynamics-mission-systems-advanced-asic-fpga-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fgeneral-dynamics-mission-systems-advanced-asic-fpga-verification-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3301587}},{"tool":"search_jobs","arguments":{"company":"gdmissionsystems.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3301587},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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