{"id":4139729,"url":"https://alion.io/job/glint-tech-solutions-physical-ic-layout-engineer-analog-pmic","title":"Physical IC Layout Engineer – Analog / PMIC","company":{"id":3854730,"name":"Glint Tech Solutions","domain":"glinttechsolutions.com","url":"https://alion.io/company/glint-tech-solutions","size_band":"11-50","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Manatal","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Edge AI","optional":false}],"status":"live","first_seen_at":"2026-11-12T04:58:17Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-12T04:58:17Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"About the Role\nWe are seeking an experienced Physical IC Layout Engineer to join our growing US-based High-Performance Computing & Edge AI Power team.\nThis role focuses on full-chip and block-level analog/power IC layout while serving as a key technical liaison between our US design engineers and China-based layout team.\nYou will contribute to next-generation power management solutions for AI data centers, high-performance computing, and advanced power delivery applications.\nKey Responsibilities\nDesign and implement full-chip and block-level physical layouts for analog, mixed-signal, and power management ICs (PMICs).\nPerform device placement and metal routing, optimizing matching, symmetry, parasitics, current density, and thermal performance.\nExecute DRC, LVS, and ERC verification, resolving layout issues to ensure manufacturability.\nCollaborate closely with analog and digital design engineers to ensure layout quality and design integrity.\nServe as the primary technical liaison between US and China engineering teams, facilitating design reviews and technical discussions in English and Mandarin.\nSupport layout development across 55nm-90nm process technologies.\nQualifications\n5+ years of hands-on IC layout experience in analog, mixed-signal, or power management IC design.\nExperience with both full-chip and block-level layout.\n Hands-on experience with 55nm-90nm process nodes (Required).\n Fluent in English and Mandarin Chinese (Required), with strong technical communication skills.\nProficiency in Cadence Virtuoso and Calibre or equivalent DRC/LVS/ERC verification tools.\nStrong understanding of device matching, guard rings, deep N-well, ESD/latch-up, electromigration, and layout-dependent effects.\nAbility to collaborate across global engineering teams and independently manage technical challenges.\nPreferred Qualifications\nExperience with 130nm or 180nm process technologies.\nFamiliarity with DC-DC converters, switching regulators, multiphase controllers, or power management IC architectures.\nPrevious experience coordinating layout development across geographically distributed teams.","description_format":"text","description_chars":2115,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[{"language":"Chinese","level":"All levels","optional":false},{"language":"English","level":"Advanced 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