{"id":4158316,"url":"https://alion.io/job/globalfoundries-3d-ic-methodology-architect","title":"3D-IC Methodology Architect","company":{"id":3730,"name":"GlobalFoundries","domain":"gf.com","url":"https://alion.io/company/globalfoundries","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":214,"ghost_share":0,"stale_share":0.958,"repost_share":0,"time_to_fill_p50_days":32,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sofia, Bulgaria"],"countries":["BG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"ANSYS","optional":false},{"name":"Ansys RedHawk","optional":false},{"name":"Cadence Allegro","optional":false},{"name":"Cadence Integrity 3D-IC","optional":false},{"name":"Linux","optional":false},{"name":"Mentor Xpedition","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys 3DIC Compiler","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimePower","optional":false},{"name":"Synopsys PrimeSim","optional":false},{"name":"Unix","optional":false},{"name":"Java","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-11-12T09:55:05Z","employer_posted_date":null,"last_verified_at":"2026-11-12T09:55:05Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, power efficient and high-performance solutions for high growth markets. With global manufacturing operations across the U.S., Europe and Asia, GF is a trusted and holistic technology partner for customers around the world. GF’s talented, global team remains focused every day on security, longevity, and sustainability. For more information, visit www.gf.com.\n\nYour Job::\n\nThe 3D-IC Methodology Architect will define and lead an integrated methodology that helps customers and internal product teams move from system architecture and chiplet planning through package co-design, multi-die implementation, multi-physics sign-off and foundry tapeout. The role combines hands-on technical depth with cross-functional leadership across design enablement, PDK and IP teams, packaging, product lines, manufacturing, OSATs and EDA partners.\n\nThe successful candidate will establish reusable reference vehicles, qualified multi-vendor flows, automation and training assets that improve design predictability, reduce late-stage rework and scale 3D-IC adoption across digital, memory, RF, silicon photonics, power and mixed-technology applications.\n\nWhat You Will Deliver \n\nReusable system-level reference examples, beginning with digital-on-digital and digital-on-memory and expanding to digital-on-IVR, RF plus digital, photonics plus CMOS and advanced stacked systems.\n\nPackage and system co-design methods for package trade studies, die-to-die planning and system-technology co-optimization.\n\nProduction-ready multi-die physical implementation flows covering floorplanning, interposer and RDL implementation, assembly definition and verification.\n\nQualified thermal, IR-drop, power-integrity and EMIR sign-off methods, progressing toward comprehensive multi-physics reliability sign-off.\n\n3D-IC PDK, reference IP, EDA-flow and automation readiness across priority technology platforms.\n\nManufacturing ready tapeout workflows across package technologies and integration options, with clear data requirements, checks and handoffs.\n\nA sustainable methodology ownership model, knowledge repository and training curriculum for internal teams and customers.\n\nEssential Responsibilities:\n\nOwn the 3D-IC methodology roadmap and translate business, product-line and customer requirements into prioritized design-flow capabilities, technical specifications and measurable qualification plans.\n\nArchitect end-to-end workflows spanning system planning, chiplet partitioning, package selection, die-to-die connectivity, implementation, verification, sign-off and tapeout.\n\nDevelop and validate reference vehicles that demonstrate foundry, EDA, IP and packaging capabilities and can be reused for customer demonstrations, training and flow qualification.\n\nLead package trade studies and establish STCO methods that connect architecture choices with process, package, power, performance, thermal, mechanical, cost and manufacturability constraints.\n\nDefine multi-die implementation methods for floorplanning, bump and interface planning, interposer/RDL routing, power delivery, assembly integration and physical verification.\n\nBuild electro-thermal and EMIR methodology for early hotspot and IR-drop detection and for sign-off correlation across chiplet, package and system boundaries.\n\nPartner with internal process/PDK, IP, substrate, packaging, manufacturing and product-line teams to define 3D-IC design-kit content and release criteria.\n\nEngage EDA vendors to close tool and interoperability gaps, qualify multi-vendor flows and influence product roadmaps. Relevant ecosystems may include Cadence Integrity 3D-IC, Allegro X, Innovus, Voltus and Celsius; Synopsys 3DIC Compiler, Fusion Compiler, RedHawk-SC, PrimePower and PrimeSim; Siemens Innovator3D IC, Xpedition, Aprisa, Calibre 3DSTACK and mPower; and Ansys Icepak and chip-package-system analysis solutions.\n\nStandardize tapeout data, assembly instructions, verification checks and cross-organizational handoffs to improve first-pass predictability and customer execution confidence.\n\nLead cross-geo technical teams, scope work packages, review technical quality, resolve ambiguity and communicate status, risks and decisions to engineering and business stakeholders.\n\nMentor engineers, establish reusable automation and regression practices, and deliver methodology documentation and training for internal users and customers.\n\nRequired Qualifications \n\nBachelor’s, Master’s or PhD degree in Electrical Engineering, Computer Engineering or a closely related discipline.\n\nTypically 15+ years of semiconductor design, design enablement, EDA methodology or related industry experience, including 10+ years in advanced design flows, IP enablement or methodology development.\n\nDemonstrated technical leadership of complex, cross-functional methodology programs involving internal teams, customers and external ecosystem partners.\n\nDeep knowledge of at least three of the following: 3D-IC or chiplet architecture, advanced packaging, multi-die physical implementation, die-to-die interfaces, thermal analysis, EMIR/power integrity, EMAG, physical verification or foundry tapeout.\n\nWorking expertise with industry-standard analog, RF, AMS and/or digital implementation and verification tools, plus the ability to define integration-level requirements across domains.\n\nExperience defining qualification criteria, creating reference designs, correlating analysis with implementation/sign-off results and deploying repeatable flows.\n\nProficiency in Linux/Unix environments and practical experience with scripting, version control, configuration management and regression infrastructure.\n\nExcellent written and verbal English communication, technical problem-solving and stakeholder-management skills.\n\nPreferred Qualifications \n\nHands-on experience with heterogeneous integration applications such as digital-on-memory, digital-on-IVR, RF plus digital, silicon photonics plus CMOS, wafer-to-wafer or die-to-wafer integration.\n\nExperience with 2.5D/3D package technologies, interposers, RDL, hybrid bonding, OSAT interfaces or substrate design and verification.\n\nUnderstanding of reliability concerns including self-heating, thermal-mechanical stress, warpage, bonding integrity and cracking risk.\n\nProgramming and automation experience in Python, Tcl, Perl, Java or comparable languages; interest in applying generative AI to methodology productivity is beneficial.\n\nExperience developing customer-facing documentation, workshops, demonstrations or training for advanced design flows.\n\nProgram or project-management skills, including milestone planning, dependency management, risk tracking and execution across ambiguous problem spaces.\n\nMeasures of Success \n\nValidated reference vehicles and a customer-demonstration platform are operational.\n\nPriority 3D-IC design kits, reference IP and partner-qualified EDA flows are released and reusable.\n\nPackage, implementation and sign-off analyses identify risks early and minimize rework between planning, implementation and tapeout.\n\nProduction workflows support multiple package technologies and provide clear, repeatable tapeout execution.\n\nA cross-functional 3D-IC methodology ownership model, knowledge repository and training curriculum are established and actively used.\n\nLeadership & Collaboration Expectations \n\nThis is a senior individual-contributor and technical-leadership role. The architect is expected to create alignment across organizations without relying solely on direct authority, make technically sound trade-offs, communicate decisions clearly, and develop the next generation of methodology talent.\n\nEnvironmental, Health, Safety & Security \n\nPerform all activities in a safe and responsible manner and support all Environmental, Health, Safety and Security requirements and programs.\n\nCandidate fit: This role is best suited to a systems-minded methodology leader who can connect semiconductor process, chiplets, packaging, EDA and manufacturing into a qualified, scalable architecture-to-tapeout platform.\n\nGlobalFoundries is committed to equal employment opportunity and maintaining a workplace free from discrimination and harassment. Employment decisions are based on legitimate, job-related criteria, including qualifications, skills, experience, performance, and business needs, and are made without regard to any characteristic protected by applicable law.\n\nAll employment policies and practices, including recruitment, selection, training, development, promotion, compensation, benefits, and termination, without regard to age, ancestry, color, disability, marital status, national origin, race, religion, sex, veteran status, or any other characteristic protected by applicable law.\n\nNo Recruitment Fee Policy: GlobalFoundries is committed to ethical and transparent hiring practices. Candidates will not be charged any fees at any stage of the recruitment process. Any request for payment related to a GlobalFoundries employment opportunity is unauthorized and should be reported immediately. All legitimate recruitment communications are conducted exclusively through official GlobalFoundries channels. To report concerns or suspected recruitment fraud, please contact our Ethics & Compliance Office at global[dot]compliance[at]globalfoundries[dot]com or visit our official website.\n\nThe Ethics & Compliance mailbox is not a recruitment channel. CVs/resumes submitted to this mailbox will not be reviewed, processed, or considered for employment opportunities. Please apply through the official GlobalFoundries careers site only.\n\nInformation about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia","description_format":"text","description_chars":9849,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductor Manufacturing"],"lifecycle":[{"event":"open","at":"2026-11-12T11:16:40Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":32,"reasons":["seen:0","win:early","comp:brand"],"computed_at":"2026-11-12T13:10:27Z"},"pay":null,"html_url":"https://alion.io/job/globalfoundries-3d-ic-methodology-architect","json_url":"https://alion.io/job/globalfoundries-3d-ic-methodology-architect.json","meta":{"generated_at":"2026-11-12T13:10:27Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":27310,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3730},"rest":"https://alion.io/mcp/rest/get_company?id=3730"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fglobalfoundries-3d-ic-methodology-architect"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fglobalfoundries-3d-ic-methodology-architect"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fglobalfoundries-3d-ic-methodology-architect"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/globalfoundries-3d-ic-methodology-architect\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fglobalfoundries-3d-ic-methodology-architect"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4158316}},{"tool":"search_jobs","arguments":{"company":"gf.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4158316},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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