{"id":3672334,"url":"https://alion.io/job/globalfoundries-digital-design-engineer","title":"Digital Design Engineer","company":{"id":3730,"name":"GlobalFoundries","domain":"gf.com","url":"https://alion.io/company/globalfoundries","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":217,"ghost_share":0,"stale_share":0.959,"repost_share":0,"time_to_fill_p50_days":32,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Egypt"],"countries":["EG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-03T09:39:47Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-04T13:16:08Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Title: Digital Design Engineer\nAbout GF\nGlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, power efficient and high-performance solutions for high growth markets. With global manufacturing operations across the U.S., Europe and Asia, GF is a trusted and holistic technology partner for customers around the world. GF’s talented, global team remains focused every day on security, longevity, and sustainability. For more information, visit www.gf.com.\nResponsibilities\nDevelop, document, and maintain RTL (SystemVerilog/Verilog) for digital subsystems within the CPO product, including control logic, register interfaces, link management, and DFT structures.\nCollaborate with architecture, analog/mixed-signal, and photonics teams to define digital interfaces and control schemes for co-packaged optical modules.\nOwn micro-architecture specifications, design reviews, and integration of digital IP into the top-level SoC.\nDrive synthesis, timing closure, CDC, lint, and low-power (UPF) sign-off in coordination with the physical design team.\nPerform FPGA prototyping and testing of digital subsystems to validate functionality, accelerate pre-silicon software bring-up, and de-risk RTL ahead of tape-out.\nDevelop and execute UVM-based testing, including building reusable verification components, writing constrained-random tests, and driving functional and code coverage closure.\nSupport verification efforts by collaborating with the DV team on testbench development, coverage closure, and debug.\nParticipate in tape-out readiness activities, including ECO planning, gate-level simulation, and post-silicon bring-up support.\nContribute to design methodology, reuse strategy, and quality improvements across the team.\n Required Qualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.\n1+ years of experience in digital RTL design using SystemVerilog/Verilog.\nSolid understanding of digital design fundamentals: synchronous design, CDC, FSMs, pipelining, and low-power techniques.\nHands-on experience with industry EDA tools (synthesis, lint, CDC, simulation).\nFamiliarity with scripting (Python, TCL, Perl) for design automation.\nStrong problem-solving skills and ability to work in a cross-functional team.\n Preferred Qualifications\nExperience with high-speed serial interfaces (SerDes, PCIe, Ethernet, CXL) or optical link control.\nExposure to silicon photonics, co-packaged optics, or advanced packaging products.\nExperience with ARM-based SoC integration, AMBA protocols (AXI/AHB/APB), and standard IP integration flows.\nPrior tape-out experience on advanced process nodes.\nKnowledge of UPF/low-power flows and DFT (scan, MBIST, boundary scan).\nWe Offer\nBase Salary\nEquity\nAnnual Bonus Plan\nMedical Insurance\nGlobalFoundries is committed to equal employment opportunity and maintaining a workplace free from discrimination and harassment. Employment decisions are based on legitimate, job-related criteria, including qualifications, skills, experience, performance, and business needs, and are made without regard to any characteristic protected by applicable law.\nAll employment policies and practices, including recruitment, selection, training, development, promotion, compensation, benefits, and termination, without regard to age, ancestry, color, disability, marital status, national origin, race, religion, sex, veteran status, or any other characteristic protected by applicable law.\nNo Recruitment Fee Policy: GlobalFoundries is committed to ethical and transparent hiring practices. Candidates will not be charged any fees at any stage of the recruitment process. Any request for payment related to a GlobalFoundries employment opportunity is unauthorized and should be reported immediately. All legitimate recruitment communications are conducted exclusively through official GlobalFoundries channels. To report concerns or suspected recruitment fraud, please contact our Ethics & Compliance Office at global[dot]compliance[at]globalfoundries[dot]com or visit our official website.\nThe Ethics & Compliance mailbox is not a recruitment channel. CVs/resumes submitted to this mailbox will not be reviewed, processed, or considered for employment opportunities. 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