{"id":2702570,"url":"https://alion.io/job/globalfoundries-pmts-asic-digital-design-ip-engineering-2","title":"PMTS ASIC Digital Design IP ENGINEERING","company":{"id":3730,"name":"GlobalFoundries","domain":"gf.com","url":"https://alion.io/company/globalfoundries","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":217,"ghost_share":0,"stale_share":0.986,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":54000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"DO-254","optional":true}],"status":"live","first_seen_at":"2026-10-16T11:36:05Z","employer_posted_date":"2026-10-16","last_verified_at":"2026-11-02T22:59:32Z","board_verified":true,"closed_at":null,"days_open":17,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":17},"description":"About GlobalFoundries:\nGlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.\nSummary of Role:\nThe PMTS Digital Design Engineer will lead the architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystem components. This role requires deep expertise in processor design, strong technical leadership, and the ability to drive complex SoC development programs from concept through silicon bring-up.\nThe candidate will work closely with architecture, verification, physical design, DFT, firmware, and software teams to deliver competitive processor products meeting performance, power, area, and schedule targets.\nEssential Responsibilities:\nProcessor Microarchitecture & RTL Design\nDevelop and implement microarchitecture for CPU cores, cache subsystems, memory management units (MMU), interconnects, and system controllers.\nTranslate architectural specifications into high-quality RTL designs using Verilog/SystemVerilog.\nDefine and review detailed design specifications, block-level architectures, and implementation strategies.\nDrive performance optimization, power reduction, and area-efficient design methodologies.\nAnalyze and resolve complex design trade-offs involving latency, throughput, and scalability.\nTechnical Leadership\nLead critical processor design initiatives across multiple functional blocks.\nMentor junior and senior engineers on microarchitecture, RTL coding practices, and design methodologies.\nConduct architecture, microarchitecture, and RTL design reviews.\nEstablish design guidelines and best practices across the organization.\nInfluence roadmap and technology decisions for future processor generations.\nCross-Functional Collaboration\nPartner with architects to evaluate new features and enhancements.\nWork closely with verification teams to define verification plans and close coverage.\nSupport synthesis, timing closure, low-power implementation, and physical design activities.\nCollaborate with DFT teams to ensure manufacturability and testability.\nSupport silicon bring-up, debug, characterization, and production ramp activities.\nPerformance Analysis & Optimization\nConduct design performance analysis and bottleneck identification.\nDrive microarchitectural enhancements to improve IPC, memory latency, and system efficiency.\nAnalyze workload behavior and benchmark performance.\nParticipate in power-performance-area (PPA) optimization efforts.\nOther Responsibilities:\nPerform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.\n\nRequired Qualifications:\nBachelor's or master's degree in electrical engineering, Computer Engineering, or related field.\n12+ years of experience in processor, CPU, DSP, or complex SoC digital design.\nDeep understanding of processor microarchitecture, including:Pipeline design\nCache architectures\nBranch prediction\nMemory hierarchy\nMMU/TLB designs\nInterrupt and exception handling\nCoherency protocols\n\nExpert-level RTL design experience using Verilog/SystemVerilog.\nStrong understanding of synthesis, timing analysis, CDC, RDC, and low-power design techniques.\nExperience with industry-standard EDA tools and design flows.\nStrong debugging and problem-solving skills.\nPreferred Qualifications\nExperience with RISC-V, ARM, MIPS, ARC, or custom CPU architectures.\nKnowledge of multi-core and heterogeneous computing systems.\nExperience in AI/ML acceleration, vector processing, or advanced computing architectures.\nExperience with performance modeling and architectural simulation.\nSilicon bring-up and post-silicon debug experience.\nExposure to safety-critical designs (ISO 26262, DO-254) is a plus.\nInformation about our benefits you can find here: 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