{"id":2263117,"url":"https://alion.io/job/globalfoundries-pmts-design-verification-lead","title":"PMTS, Design Verification Lead","company":{"id":3730,"name":"GlobalFoundries","domain":"gf.com","url":"https://alion.io/company/globalfoundries","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":188,"ghost_share":0,"stale_share":0.984,"repost_share":0,"time_to_fill_p50_days":31,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Design","role_family":"Design","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":54000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-08-10T00:00:00Z","employer_posted_date":"2026-08-10","last_verified_at":"2026-10-23T16:46:08Z","board_verified":true,"closed_at":null,"days_open":74,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":74},"description":"Title: PMTS, Design Verification Lead\nAbout GlobalFoundries\nGlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.\nIntroduction:\nWe are seeking an experienced Design Verification Lead to drive verification strategy, planning, execution, and signoff for next-generation RISC-V based Processor IP products. The successful candidate will lead a team of verification engineers responsible for ensuring functional correctness, quality, performance, safety, and robustness of complex processor subsystems and full-chip IP solutions.\nThis role requires strong technical leadership, deep expertise in processor architecture verification, and proven experience delivering high-quality silicon-proven IP products from specification through production release.\nKey Responsibilities\nTechnical Leadership\nOwn the verification strategy and verification signoff for processor IP products and subsystems.\nLead verification planning, methodology definition, execution, and closure activities.\nDefine coverage goals, quality metrics, signoff criteria, and verification milestones.\nDrive verification readiness reviews, risk assessments, and program execution.\nProvide technical direction and mentorship to verification engineers across multiple projects.\nVerification Architecture & Methodology\nArchitect scalable verification environments using SystemVerilog, UVM, assertions, and constrained-random methodologies.\nDefine reusable verification infrastructure across multiple processor families.\nEstablish methodology standards, coding guidelines, and best practices.\nDrive adoption of advanced verification techniques including formal verification, emulation, FPGA prototyping, and hardware/software co-verification.\nProcessor Verification\nLead verification of CPU cores, DSP extensions, vector processing units, MMUs, caches, interrupts, debug infrastructure, security features, and system interfaces.\nDrive ISA compliance verification and architectural validation.\nOversee development of directed, random, compliance, and software-driven test suites.\nCollaborate closely with architecture and design teams to ensure comprehensive verification coverage.\nProject Execution\nOwn verification schedules, resource planning, and execution tracking.\nDrive bug triage, root-cause analysis, and closure activities.\nEnsure verification deliverables meet quality, schedule, and product objectives.\nPresent status, risks, and signoff readiness to executive leadership.\nCross-Functional Collaboration\nPartner with architecture, RTL design, validation, emulation, FPGA, functional safety, and software teams.\nParticipate in requirements analysis and verification planning activities.\nSupport customer engagements, technical reviews, audits, and product bring-up activities.\nQuality & Signoff\nOwn functional, code, assertion, and architectural coverage closure.\nReview verification plans, testbenches, and verification reports.\nEnsure compliance with product development and quality management processes.\nDrive continuous improvement of verification productivity and quality.\nRequired Qualifications\nBS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.\nTypically 12+ years of relevant industry experience in ASIC/SoC/Processor verification.\nProven track record leading verification teams for complex CPU, MCU, DSP, or Processor IP products.\nExpert knowledge of:SystemVerilog\nUVM\nAssertions (SVA)\nFunctional Coverage\nConstrained Random Verification\n\nStrong understanding of processor architectures and microarchitecture concepts.\nExperience with:RISC-V, ARM, or equivalent processor architectures\nSimulation, emulation, and regression infrastructures\nCoverage-driven verification\nVerification signoff methodologies\n\nExcellent project leadership and communication skills.\nPreferred Qualifications\nExperience verifying:RISC-V processors\nVector extensions\nDSP architectures\nFunctional safety, Cyber Security products (ISO 26262, ISO 21434)\nSecurity, Security architectures\n\nExperience with:Building env from scratch\nFormal verification\nEmulation platforms\nFPGA prototyping\nPerformance verification\nSoftware-driven verification\n\nPrior people leadership or technical leadership of globally distributed teams.\nGlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.\nAs an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.\nAll offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.\nInformation about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia","description_format":"text","description_chars":5406,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Manufacturing","Electrical & Electronic Engineering","Semiconductor Manufacturing"],"lifecycle":[{"event":"open","at":"2026-10-11T05:33:41Z"}],"visa":[],"liveness":{"score":11,"band":"cold","label":"Long shot","p_open":1,"p_active":0.403,"p_room":0.28,"age_days":74,"expected_fill_days":31,"reasons":["conf:0","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/globalfoundries-pmts-design-verification-lead","json_url":"https://alion.io/job/globalfoundries-pmts-design-verification-lead.json","meta":{"generated_at":"2026-10-23T17:23:05Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":26390,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3730},"rest":"https://alion.io/mcp/rest/get_company?id=3730"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fglobalfoundries-pmts-design-verification-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fglobalfoundries-pmts-design-verification-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fglobalfoundries-pmts-design-verification-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/globalfoundries-pmts-design-verification-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fglobalfoundries-pmts-design-verification-lead"}]}