{"id":2263055,"url":"https://alion.io/job/globalfoundries-principal-engineer-soc-design-lead","title":"Principal Engineer SoC Design Lead","company":{"id":3730,"name":"GlobalFoundries","domain":"gf.com","url":"https://alion.io/company/globalfoundries","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":217,"ghost_share":0,"stale_share":0.986,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":60000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-27T00:00:00Z","employer_posted_date":"2026-08-27","last_verified_at":"2026-11-02T13:18:32Z","board_verified":true,"closed_at":null,"days_open":67,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":67},"description":"Principal SoC Design Lead\nAbout GlobalFoundries\nGlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.\nBuild the Next Generation of Advanced Sensor Platforms at GF\nAt MIPS by GF Custom Silicon Business, we are developing highly integrated Advanced Sensor Platform solutions that combine compute, signal processing, connectivity, security, safety, and software into differentiated semiconductor products for our customers.\nOur teams span architecture, modeling, RTL development, verification, physical implementation, software, test, and product engineering. We bring together experts from multiple disciplines to solve challenging power, performance, area, safety, security, and cost optimization problems while delivering highly scalable and reusable platform solutions.\nIntroduction:\nThe Principal SoC Design Lead is responsible for the architecture, microarchitecture, integration, and delivery of complex SoCs for Smart Analog & Sensor products. This individual serves as the technical leader for one or more SoC programs, driving IP integration, subsystem development, RTL quality, and cross-functional execution from concept through silicon.\nThe role requires strong expertise in processor-based SoCs, subsystem architecture, RTL development, and SoC integration, combined with the ability to lead technical teams across multiple disciplines.\nWe are seeking seasoned SoC Design / RTL Lead who combines strong architectural vision with deep hands-on RTL experience. The successful candidate will play a pivotal role in defining and delivering next-generation platform architectures that enable multiple customer products and future derivatives.\nJoin us and put your skills, insight, and passion to redefine what’s possible.\nKey Responsibilities\nAs a SoC Design / RTL Lead, you will own or participate in the following:\nDefinition and ownership of SoC architecture spanning processing subsystems, memory hierarchy, NoC/interconnect, clocking, reset, interrupt and event infrastructure, interfaces, and peripherals.\n\nDevelopment of microarchitectural specifications from architectural exploration through implementation-ready design specifications\n\nOwnership of system-level performance, power and area tradeoffs\n\nDefinition and integration of subsystem interfaces across compute, datapath, safety, security, software and peripheral domains\n\nTechnical leadership of RTL implementation teams and convergence of architecture into production-quality RTL\n\nCollaboration with verification, DFT and physical design teams to achieve project objectives\n\nContribute to platform roadmaps and reusable SoC architectures\n\nReview microarchitecture and RTL implementation of critical blocks.\n\nDrive issue resolution across architecture, RTL, DV, DFT, and Physical Design teams.\n\nEvaluate, select, and integrate internal and third-party IP and establish IP reuse methodologies\n\nDrive closure of functionality, timing, power, and integration objectives.\n\nSupport post-silicon debug and root-cause analysis.\n\nMentor RTL and integration engineers.\n\nLead technical reviews and design signoffs.\n\nInfluence engineering methodology and best practices across the organization.\n\nKey responsibilities\nSoC Architecture & Planning\nDefine SoC and subsystem architectures aligned with product requirements.\n\nDrive hardware partitioning across processors, accelerators, memories, and peripherals.\n\nLead architecture tradeoff analyses covering performance, power, area, safety, and scalability.\n\nContribute to platform roadmaps and reusable SoC architectures.\n\nRTL & Integration Leadership\nLead development of complex RTL subsystems and top-level integration.\n\nDefine SoC integration methodologies and quality standards.\n\nReview microarchitecture and RTL implementation of critical blocks.\n\nDrive issue resolution across architecture, RTL, DV, DFT, and Physical Design teams.\n\nIP Strategy\nEvaluate, select, and integrate internal and third-party IP.\n\nEstablish IP reuse methodologies across multiple product generations.\n\nEnsure robust SoC assembly and subsystem interoperability.\n\nSilicon Execution\nLead execution from specification through tapeout and silicon bring-up.\n\nDrive closure of functionality, timing, power, and integration objectives.\n\nSupport post-silicon debug and root-cause analysis.\n\nTechnical Leadership\nMentor RTL and integration engineers.\n\nLead technical reviews and design signoffs.\n\nInfluence engineering methodology and best practices across the organization.\n\nMinimum Qualifications\nMinimum BS and 15+ years of relevant industry experience\n\nExperience architecting and delivering complex SoCs\n\nExperience with memory hierarchies, NoCs, bus architectures and system integration\n\nExpertise in RTL development using Verilog or SystemVerilog\n\nExperience with architecture-performance-power-area tradeoff analysis\n\nPreferred Qualifications\nExperience with automotive or safety-critical systems\n\nExperience with multicore systems\n\nExperience with security and functional safety architectures\n\nExperience leading cross-functional engineering teams\n\nExperience with advanced implementation and signoff flows\n\nGlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.\nAs an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.\nAll offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.\nInformation about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia","description_format":"text","description_chars":6295,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Manufacturing","Electrical & Electronic Engineering","Semiconductor Manufacturing"],"lifecycle":[{"event":"open","at":"2026-10-11T05:33:41Z"}],"visa":[],"liveness":{"score":13,"band":"cold","label":"Long shot","p_open":1,"p_active":0.473,"p_room":0.28,"age_days":67,"expected_fill_days":30,"reasons":["conf:8","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-11-02T06:13:15Z"},"pay":null,"html_url":"https://alion.io/job/globalfoundries-principal-engineer-soc-design-lead","json_url":"https://alion.io/job/globalfoundries-principal-engineer-soc-design-lead.json","meta":{"generated_at":"2026-11-02T18:28:15Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":25843,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-03T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3730},"rest":"https://alion.io/mcp/rest/get_company?id=3730"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fglobalfoundries-principal-engineer-soc-design-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fglobalfoundries-principal-engineer-soc-design-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fglobalfoundries-principal-engineer-soc-design-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/globalfoundries-principal-engineer-soc-design-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fglobalfoundries-principal-engineer-soc-design-lead"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2263055}},{"tool":"search_jobs","arguments":{"company":"gf.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2263055},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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