{"id":1277780,"url":"https://alion.io/job/google-asic-design-verification-engineer-digital-signal-processing","title":"ASIC Design Verification Engineer, Digital Signal Processing","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":110,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-07T05:47:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":135000,"max_usd":253000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1119},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Edge AI","optional":false},{"name":"GCP","optional":false},{"name":"MATLAB","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TPU","optional":false},{"name":"UVM","optional":false},{"name":"Vertex AI","optional":false}],"status":"live","first_seen_at":"2026-09-16T11:37:50Z","employer_posted_date":"2026-10-04","last_verified_at":"2026-10-07T23:32:44Z","board_verified":true,"closed_at":null,"days_open":21,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":21},"description":"About the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.\nIn this role, you will define and execute the verification strategy for high-speed Physical Layer (PHY) digital blocks. This role focuses on the functional and mathematical verification of complex DSP algorithms, digital-analog boundaries, and signal processing logic. This position requires a strong technical foundation in communication theory, fixed-point arithmetic, and mixed-signal co-simulation.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\n Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nVerify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.\nVerify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.\nModel and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or SystemVerilog-AMS.\nDesign, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.\n8 years of experience in design verification (DV) with a focus on digital signal processing (DSP), communication systems, or arithmetic logic blocks.\nExperience with scripting in Python, Perl, or Makefile for automation.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.\nExperience with Mixed-Signal verification techniques such as Real Number Modeling (RNM, SystemVerilog-Wreal) or SystemVerilog-AMS.\nFunctional knowledge of adaptive equalization architectures (FFE/DFE) and timing recovery loops.\nProgramming proficiency in Python, MATLAB, or C/C++ for testbench automation and reference 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