{"id":1290659,"url":"https://alion.io/job/google-asic-design-verification-engineer-machine-learning","title":"ASIC Design Verification Engineer, Machine Learning","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":78,"open_postings":134,"ghost_share":0.045,"stale_share":0.739,"repost_share":0.045,"time_to_fill_p50_days":30,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":146000,"max_usd":270000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1517},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"GCP","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TPU","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Vertex AI","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-01-21T16:29:28Z","employer_posted_date":"2026-11-06","last_verified_at":"2026-11-07T16:44:00Z","board_verified":true,"closed_at":null,"days_open":290,"trust":{"level":"stale","repost_count":1,"flags":["stale"],"days_open":289},"description":"About the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.\nAs an ASIC Design Verification Engineer, you will use design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform direct verification. Using SystemVerilog coding and problem-solving skills, you will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full lifecycle of verification, from verification planning to test execution, to collecting and closing coverage.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\nIndividual pay is determined by factors including job-related skills, experience, and relevant education or training.\nUS: $138000 - $198000 (USD) + 15% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nPlan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.\nCreate and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.\nIdentify and write all types of coverage measures for stimulus and corner-cases.\nDebug tests with design engineers to deliver functionally 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