{"id":2033941,"url":"https://alion.io/job/google-asic-design-verification-technical-lead-high-speed-dsp","title":"ASIC Design Verification Technical Lead, High-Speed DSP","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":83,"open_postings":172,"ghost_share":0.041,"stale_share":0.57,"repost_share":0.041,"time_to_fill_p50_days":30,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":181000,"max_usd":336000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":656},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"GCP","optional":false},{"name":"Quantization","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TPU","optional":false},{"name":"UVM","optional":false},{"name":"Vertex AI","optional":false}],"status":"live","first_seen_at":"2026-10-07T14:08:00Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-10-27T04:15:10Z","board_verified":true,"closed_at":null,"days_open":19,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":19},"description":"About the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.As an ASIC Design Verification Technical Lead, you will define how Google verifies the physical-layer Digital Signal Processing (DSP) pipelines powering our next-generation AI hardware accelerators. You will drive the shift toward Emulation and Post-Silicon Correlation, ensuring that our architectural reference models and pre-silicon simulations perfectly match the physical behavior of the high-speed silicon in our planetary-scale AI data centers.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\n Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nDesign, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks.\nBuild co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models.\nDefine and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows.\nAuthor dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles.\nLead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.\n12 years of experience in design verification.\nExperience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.\nExperience defining verification architectures, methodologies, and roadmaps for AI accelerators, High-Performance Computing or high-bandwidth networking silicon.\nExperience bridging the gap between Pre-Silicon verification (simulation and emulation) and Post-Silicon validation and correlation.\nExperience driving advanced verification methodologies.","description_format":"text","description_chars":3777,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Streaming & OTT Platforms","Foundation Models","Consumer Internet Groups"],"lifecycle":[{"event":"open","at":"2026-10-07T15:15:45Z"}],"visa":[],"liveness":{"score":50,"band":"ok","label":"Likely open","p_open":1,"p_active":0.559,"p_room":0.9,"age_days":18,"expected_fill_days":30,"reasons":["conf:3","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-26T05:57:25Z"},"pay":null,"html_url":"https://alion.io/job/google-asic-design-verification-technical-lead-high-speed-dsp","json_url":"https://alion.io/job/google-asic-design-verification-technical-lead-high-speed-dsp.json","meta":{"generated_at":"2026-10-27T05:22:55Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":5169,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":82},"rest":"https://alion.io/mcp/rest/get_company?id=82"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fgoogle-asic-design-verification-technical-lead-high-speed-dsp"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fgoogle-asic-design-verification-technical-lead-high-speed-dsp"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fgoogle-asic-design-verification-technical-lead-high-speed-dsp"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/google-asic-design-verification-technical-lead-high-speed-dsp\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fgoogle-asic-design-verification-technical-lead-high-speed-dsp"}]}