{"id":2732316,"url":"https://alion.io/job/google-chip-package-signal-and-power-integrity-engineer-2","title":"Chip Package Signal and Power Integrity Engineer","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":84,"open_postings":184,"ghost_share":0.038,"stale_share":0.538,"repost_share":0.038,"time_to_fill_p50_days":30,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":115000,"max_usd":218000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":5966},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys SIwave","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"GCP","optional":false},{"name":"HPC","optional":false},{"name":"TPU","optional":false},{"name":"Vertex AI","optional":false},{"name":"C++","optional":true},{"name":"MATLAB","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-16T17:09:27Z","employer_posted_date":"2026-10-16","last_verified_at":"2026-10-23T21:03:43Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"About the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.\nAs a Signal Integrity/Power Integrity Engineer, you'll lead chip and package design, ensuring optimal SI/PI performance and system co-design from concept to production. Collaborating within a cross-functional team, including Chip Design, IP, System Design, software, and vendors, you'll drive signal and power design implementations on chip and advanced packages.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\n Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nLead SI/PI analysis for High-Performance Computing (HPC) utilizing 2.5D/3D package technologies to define specifications and optimize chip floorplans, power trees, and netlists.\nDrive next-generation memory interface development and evaluate high-speed Interface IPs, balancing complex trade-offs across IO PHY, SI/PI, and physical design.\nOwn post-silicon validation and qualification of high-speed interfaces to ensure successful New Product Introduction (NPI).\nPartner with chip/system design teams, suppliers, and vendors to establish SI/PI goals, define design boundaries, and manage DFM trade-offs.\nProvide crucial feedback on chip floorplans to maximize package/system routability and SI/PI, while developing methodologies to improve simulation accuracy and productivity.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\n7 years of experience with SI/PI design for chip/package or system PCB.\n\nExperience in industry Signal integrity and Power Integrity (SIPI) modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).\nPreferred qualifications:\nMaster’s degree or PhD in Electrical Engineering or SI/PI.\nExperience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, and expertise in SI/PI analysis for high-speed interconnects.\n Knowledge of next-generation memory and chiplet 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