{"id":1278174,"url":"https://alion.io/job/google-cpu-emulation-engineer-silicon","title":"CPU Emulation Engineer, Silicon","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":117,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-09-28T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":126000,"max_usd":235000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":910},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Cadence Protium","optional":false},{"name":"CI/CD","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Veloce","optional":false},{"name":"Synopsys HAPS","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-12T08:50:40Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-26T21:50:13Z","board_verified":false,"closed_at":null,"days_open":47,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":47},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.\nUS: $163000 - $236000 (USD) + 15% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nArchitect and drive advanced Register-Transfer Level (RTL) partitioning, Field-Programmable Gate Array (FPGA) synthesis, and validation strategies for industry-standard emulation platforms such as Synopsys ZeBu, Cadence Palladium, or Siemens Veloce.\nDefine and execute comprehensive test suites, complex performance benchmarks, and software workloads to ensure pre-silicon verification and system-level validation.\nGuide advanced debugging methodologies to rapidly isolate and resolve complex functional failures within multi-million gate subsystem designs and full-chip environments.\nLead initiatives to optimize model compile times, improve FPGA routing efficiency, and maximize hardware resource utilization across enterprise emulation farms.\nArchitect custom automation workflows using modern scripting languages and collaborate with IP design and verification stakeholders to streamline continuous integration.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.\n8 years of experience with industry-standard emulation or FPGA prototyping platforms (e.g., Synopsys ZeBu/HAPS, Cadence Palladium/Protium, Siemens Veloce).\nExperience in RTL design using Verilog or SystemVerilog.\nExperience writing scripts or developing automation workflows in Python, Perl, TCL, or Makefiles.\nPreferred qualifications:\nExperience scaling compilation and routing across multi-FPGA and enterprise emulation platforms.\nExperience verifying and troubleshooting complex semiconductor IP blocks.\nExperience collaborating with cross-functional design verification (DV) and silicon design teams.","description_format":"text","description_chars":2691,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Streaming & OTT Platforms","Foundation Models","Consumer Internet Groups"],"lifecycle":[{"event":"open","at":"2026-09-26T02:15:01Z"}],"liveness":{"score":15,"band":"cold","label":"Long shot","p_open":1,"p_active":0.336,"p_room":0.45,"age_days":46,"expected_fill_days":30,"reasons":["conf:31","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-09-28T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/google-cpu-emulation-engineer-silicon","json_url":"https://alion.io/job/google-cpu-emulation-engineer-silicon.json","meta":{"generated_at":"2026-09-28T23:14:43Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":813,"day_limit":5000,"remaining_today":4187,"minute_limit":60,"resets_at":"2026-09-29T00:00:00Z"}}}