{"id":1237983,"url":"https://alion.io/job/google-low-power-verification-engineer-physical-design","title":"Low Power Verification Engineer, Physical Design","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":117,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-09-28T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":140000,"max_usd":263000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":910},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Edge AI","optional":false},{"name":"GCP","optional":false},{"name":"TPU","optional":false},{"name":"Vertex AI","optional":false},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-23T16:09:00Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-09-26T21:50:13Z","board_verified":false,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"About the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\n Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nDesign, deploy, and carry out post-layout low power verification methodologies according to execution schedules and tapeout signoff criteria to ensure successful multi-voltage implementation.\nValidate the implementation of complex multi-voltage design collateral, performing gate-level checks using industry-standard tools (e.g., Synopsys VCLP) to ensure power/ground integrity and Unified Power Format (UPF) alignment.\nDrive the resolution of complex Physical Design and Place & Route (P&R) anomalies, specifically mitigating issues such as wrong domain buffering, secondary power routing failures, and isolation clamping errors.\nPerform debugging on advanced Clock Tree Synthesis (CTS) implementations, analyzing tool behavior around level shifters in high fanout networks, duty cycle distortions, and multi-voltage skew management.\nDrive the continuous refinement of power state tables (PST) and Unified Power Format (UPF) scripts to ensure accurate translation from Golden RTL to the final physical netlist.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.\n8 years of experience performing post-layout physical netlist validation and low-power signoff within advanced ASIC design workflows.\nExperience with static low-power rule-checking tools (such as VCLP or CLP), including experience in debugging structural checks and signal corruption issues.\nExperience validating special low-power components (isolation cells, power switches, level shifters, retention registers, and always-on cells) across all stages from synthesis to place and route.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.\nExperience with scripting languages (e.g., Tcl or Python) to automate Engineering Change Orders (ECOs) and improve verification workflows.\nExperience interacting with P&R tools (Innovus, Fusion) and an understanding of standard cell timing, hierarchical construction, and physical logic optimization.\nExperience with UPF implementation, low-power architecture design, and resolving low-power check violations.\n\nExpertise in resolving technical issues within the IEEE 1801 UPF framework and physical gate-level netlist flow.\n\nFamiliarity with timing-driven Place and Route, including insertion, scaling, level shifters, and always-on cells.","description_format":"text","description_chars":4162,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Streaming & OTT Platforms","Foundation Models","Consumer Internet Groups"],"lifecycle":[{"event":"open","at":"2026-09-25T16:14:42Z"}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":4,"expected_fill_days":30,"reasons":["conf:31","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-09-28T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/google-low-power-verification-engineer-physical-design","json_url":"https://alion.io/job/google-low-power-verification-engineer-physical-design.json","meta":{"generated_at":"2026-09-29T01:58:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1632,"day_limit":5000,"remaining_today":3368,"minute_limit":60,"resets_at":"2026-09-30T00:00:00Z"}}}