{"id":1290434,"url":"https://alion.io/job/google-rtl-design-engineer-google-cloud","title":"RTL Design Engineer, Google Cloud","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":117,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-09-27T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tel Aviv, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":85000,"max_usd":184000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":438},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"GCP","optional":false},{"name":"Gemini","optional":false},{"name":"Machine Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TPU","optional":false},{"name":"Verilog","optional":false},{"name":"Vertex AI","optional":false},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-09T14:37:04Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-26T21:50:13Z","board_verified":true,"closed_at":null,"days_open":18,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":18},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.\nIn this role, you will use Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This includes creating IP Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies, including design generation automation. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing, etc. You will develop/define design options for performance, power and area.\nThe ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.\nWe prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.\nResponsibilities\nDefine the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.\nPerform RTL development (coding and debug in Verilog, SystemVerilog).\nConduct function/performance simulation debug and Lint/CDC/FV/UPF checks.\nEngage in synthesis, timing/power closure, and ASIC silicon bring-up.\nContribute to verification test plan and coverage analysis of block and SoC-level.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.\n4 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.\nExperience in logic design and debug with Design Verification (DV).\nExperience with microarchitecture and specifications.\nPreferred qualifications:\nExperience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.\nExperience with design sign off and quality tools (e.g., Lint, CDC, VCLP, etc.).\nExperience in a scripting language like Python or Perl.\nKnowledge of SoC architecture and assertion-based formal verification.\nKnowledge of one of these areas, PCIe, UCIe, DDR, AXI, ARM processors family.\nKnowledge of high performance and low power design techniques.","description_format":"text","description_chars":3170,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Streaming & OTT Platforms","Foundation Models","Consumer Internet Groups"],"lifecycle":[{"event":"open","at":"2026-09-26T07:46:53Z"}],"liveness":{"score":33,"band":"fade","label":"Fading","p_open":1,"p_active":0.366,"p_room":0.9,"age_days":17,"expected_fill_days":30,"reasons":["conf:7","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-09-27T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/google-rtl-design-engineer-google-cloud","json_url":"https://alion.io/job/google-rtl-design-engineer-google-cloud.json","meta":{"generated_at":"2026-09-28T05:14:32Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3437,"day_limit":5000,"remaining_today":1563,"minute_limit":60,"resets_at":"2026-09-29T00:00:00Z"}}}