{"id":2929962,"url":"https://alion.io/job/google-senior-ddr-design-verification-engineer-google-cloud-2","title":"Senior DDR Design Verification Engineer, Google Cloud","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":38,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tel Aviv, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":100000,"max_usd":231000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1777},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"GCP","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TPU","optional":false},{"name":"UVM","optional":false},{"name":"Vertex AI","optional":false}],"status":"live","first_seen_at":"2026-10-20T08:09:18Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T12:21:14Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.\nIn this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing. You will verify digital designs, collaborate closely with colleagues on projects, and perform direct validation. You will construct testbenches that exercise hardware through corner-cases and expose bugs. You will manage the full life-cycle from planning and execution to closing coverage.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\n Responsibilities\nPlan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.\nCreate and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.\nIdentify and write all types of coverage measures for corner-cases.\nDebug tests with design engineers to deliver functionally correct design blocks.\nClose coverage measures to identify verification holes and to show progress towards tape-out.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering or equivalent practical experience.\n8 years of experience with creating and using verification components and environments in standard verification methodology.\nExperience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, or a related field.\nExperience with verification techniques, and the full verification life cycle.\nExperience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.\nExperience with performance verification of ASICs and ASIC components.\nExperience in DDR PHY/Controller verification activities.\nExperience in DDR SoC integration and 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