{"id":1290744,"url":"https://alion.io/job/google-senior-design-engineer-networking-google-cloud","title":"Senior Design Engineer, Networking, Google Cloud","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":92,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Frontend","role_family":"Frontend","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Haifa, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Edge AI","optional":false},{"name":"GCP","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TPU","optional":false},{"name":"Verilog","optional":false},{"name":"Vertex AI","optional":false},{"name":"VHDL","optional":false},{"name":"C++","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-07T13:37:31Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-01T16:41:36Z","board_verified":true,"closed_at":null,"days_open":24,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":24},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\n Responsibilities\nDefine the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.\nPerform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHSIC Hardware Description Language (VHDL)), function/performance simulation debug, and Lint/CDC/FV/UPF checks.\nParticipate in synthesis, timing/power, and FPGA/silicon bring-up.\nParticipate in test plan and coverage analysis of the block and SOC-level verification.\nCommunicate and work with multi-disciplined and multi-site teams.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\n8 years of experience architecting networking ASICs from specification to production or equivalent experience.\nExperience developing RTL for ASIC subsystems.\nExperience in micro-architecture, design, verification, logic synthesis, and timing closure.\nPreferred qualifications:\nExperience working with design networking: Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.\nExperience architecting networking switches, end points, and hardware offloads.\nExperience working with software teams optimizing the hardware/software interface.\nExperience in a procedural programming language (e.g., C++, Python, Go).\nKnowledge of TCP, IP, Ethernet, PCIE and DRAM.\nFamiliarity with Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).","description_format":"text","description_chars":2791,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Streaming & OTT Platforms","Foundation Models","Consumer Internet Groups"],"lifecycle":[{"event":"open","at":"2026-09-26T07:46:53Z"}],"liveness":{"score":32,"band":"fade","label":"Fading","p_open":1,"p_active":0.431,"p_room":0.75,"age_days":23,"expected_fill_days":29,"reasons":["conf:8","stale_co","velocity","win:late","comp:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/google-senior-design-engineer-networking-google-cloud","json_url":"https://alion.io/job/google-senior-design-engineer-networking-google-cloud.json","meta":{"generated_at":"2026-10-01T21:16:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3901,"day_limit":5000,"remaining_today":1099,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}