{"id":1315598,"url":"https://alion.io/job/google-senior-design-engineer-rtl","title":"Senior Design Engineer, RTL","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Mountain View, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":131000,"max_usd":241000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":700},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-08-12T22:08:33Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-26T21:50:13Z","board_verified":true,"closed_at":null,"days_open":45,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":45},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.\nGoogle's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.\nIndividual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nDefine the detailed microarchitecture specifications for silicon subsystems and small to medium-sized intellectual property blocks to meet performance, area, and power requirements.\nIntegrate internal and external intellectual property (IP) blocks seamlessly into complex silicon designs and multi-component subsystems.\nExecute production-grade RTL coding, debug intricate function and performance simulation issues, and conduct standard lint, clock domain crossing, formal verification, and unified power format checks.\nPartner closely with validation teams during test plan formulation and coverage analysis for comprehensive subsystem and chip-level design verification.\nDrive technical alignment across multi-disciplinary and multi-site engineering groups to resolve architectural issues and ensure successful product delivery.\n\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\n8 years of experience with IP Development or Integration.\nExperience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).\nExperience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.\nExperience with ASIC design methodologies for clock domain checks, reset checks, and low power design.\nKnowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.\nKnowledge of high-performance and low-power design techniques.\nKnowledge of ASIC Verification, DFT, synthesis, STA, or physical design.\nKnowledge of FPGA and emulation platforms.","description_format":"text","description_chars":2796,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Streaming & OTT Platforms","Foundation Models","Consumer Internet Groups"],"lifecycle":[{"event":"open","at":"2026-09-26T18:20:57Z"}],"liveness":{"score":17,"band":"cold","label":"Long shot","p_open":1,"p_active":0.461,"p_room":0.36,"age_days":45,"expected_fill_days":30,"reasons":["conf:3","win:tail","crowd:brand"],"computed_at":"2026-09-27T01:01:07Z"},"pay":null,"html_url":"https://alion.io/job/google-senior-design-engineer-rtl","json_url":"https://alion.io/job/google-senior-design-engineer-rtl.json","meta":{"generated_at":"2026-09-27T01:01:07Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":916,"day_limit":5000,"remaining_today":4084,"minute_limit":60,"resets_at":"2026-09-28T00:00:00Z"}}}