{"id":3301738,"url":"https://alion.io/job/google-senior-full-custom-silicon-analog-design-engineer-raxium","title":"Senior Full-Custom Silicon Analog Design Engineer, Raxium","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":79,"open_postings":143,"ghost_share":0.049,"stale_share":0.678,"repost_share":0.049,"time_to_fill_p50_days":30,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Fremont, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":142000,"max_usd":261000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1517},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Siemens Calibre","optional":false},{"name":"Synopsys HSPICE","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"closed","first_seen_at":"2026-10-26T18:13:27Z","employer_posted_date":"2026-10-26","last_verified_at":"2026-11-02T13:04:27Z","board_verified":false,"closed_at":"2026-11-02T13:04:27Z","days_open":6,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":6},"description":"About the job\nWe are seeking a highly skilled and experienced Senior Full-Custom Silicon Analog Design Engineer with customer-owned tooling (COT) and complementary metal-oxide semiconductor (CMOS) expertise to join our dynamic team and develop the next generation of our cutting-edge silicon for MicroLED-based microdisplay CMOS backplane.In this role, you will be responsible for the design, simulation, and guide the layout of high-performance analog and mixed-signal circuits in advanced CMOS technologies. You will play a key role in the development of next-generation products, contributing to all phases of the analog custom design from concept to production.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.\nUS: $192000 - $278000 (USD) + 20% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nLead end-to-end full-custom analog modules, encompassing analog IP specifications, architectural definition, seamless integration, and extensive transistor-level design and simulation.\nParticipate in full-chip integration and full-custom Pixel Array IP creation, architecting specialized MicroLED drivers for individual pixel diodes and meeting constraints.\nDrive transistor-level innovations for ultra-low-power and low-voltage operation across custom logic, standard cells, and ultra-low-power Static Random-Access Memory (SRAM) memory blocks, reducing active and standby power dissipation.\nDirect physical layout guidance and parasitic optimization. Partner closely with layout designers on critical floorplanning, symmetry, shielding, matching, and electromigration/IR-drop sign-off.\nCollaborate closely with RTL designers, micro-architecture teams, and mixed-mode simulation groups using advanced modeling (Verilog-AMS, SystemVerilog RNM) to optimize chip performance, while co-leading post-tapeout silicon bench characterization and debug.\nQualifications\nMinimum qualifications:\nBachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.\n8 years of full-custom SOC design experience.\nExperience supporting tape-outs of analog and mixed-signal circuits in advanced CMOS nodes (e.g., 22nm, 12nm, FinFET).\nExperience with standard electronic design automation (EDA) layout, parasitic extraction, and schematic simulation tools (e.g., Virtuoso, Spectre, Calibre, Primsim, or HSPICE).\nExperience with transistor-level design of full-custom analog modules.\nPreferred qualifications:\nMaster’s degree or PhD in Electrical Engineering or related field.\nExperience in full-custom Pixel Array IP creation, MicroLED or display backplanes, and active-matrix architectures.\nExperience in Silicon Memory Implementation like Static Random Access Memory (SRAM) cell design or low-power memory structures.\nExperience in ultra-low-power management systems, including regulators and charge pumps.\nExperience with patented technology or publications in conferences or journals.\nExperience using AI for analog design.","description_format":"text","description_chars":3567,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Internet Services","Digital Storage","Digital Media","Marketing Analytics & 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