{"id":2369341,"url":"https://alion.io/job/google-senior-hardware-emulation-engineer-google-cloud","title":"Senior Hardware Emulation Engineer, Google Cloud","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":114,"ghost_share":0,"stale_share":0.982,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":140000,"max_usd":262000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1211},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Cadence Palladium","optional":false},{"name":"CI/CD","optional":false},{"name":"Edge AI","optional":false},{"name":"GCP","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Shift-Left","optional":false},{"name":"Shift-Left Security","optional":false},{"name":"Siemens Veloce","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TPU","optional":false},{"name":"Verilog","optional":false},{"name":"Vertex AI","optional":false}],"status":"closed","first_seen_at":"2026-10-12T13:38:43Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-13T00:55:28Z","board_verified":false,"closed_at":"2026-10-13T00:55:28Z","days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"About the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.\nIn this role, you will help develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our ASIC projects.You will help create ASICs representing a significant investment in time and money, and a successful prototyping campaign helps to ensure success of these critical projects. However, as designs continue to increase in size and complexity, emulation becomes even more important in meeting verification and bring-up milestones. You will provide excellent emulation infrastructure and methodologies essential to support these projects.\nYou will work directly with other emulation team members as well as designers, verification engineers, and software teams. You will compile complex projects targeting our platforms, bring up high-speed interfaces, debug issues across design and infrastructure, and help drive pre-silicon and lab bring-up and validation of our ASIC systems.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\n Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nBuild, compile, and debug full-chip and multi-die System-on-Chip (SoC) RTL models and tests on hardware emulation platforms.\nBring up external interfaces (e.g., PCIe, HBM, DDR5, UCIe, Ethernet, USB) on emulation platforms using transactors, Accelerated VIPs, and speed bridges.\nExplore verification and emulation methodologies, gather feedback and implement new emulation workflows and CI/CD automation.\nPartner with firmware, system software, and post-silicon validation teams to drive pre-silicon hardware/software co-verification, shift-left software bring-up, and silicon bug reproduction on emulation.\nSupport emulation and software team members in debugging hardware, tooling, compile, and runtime issues, and act as a technical interface to emulation vendors.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.\n8 years of experience with hardware emulation systems (e.g., Palladium, ZeBu, Veloce), model compilation, runtime performance optimization, and methodology enhancements across ASIC programs.\nExperience integrating and debugging high-speed protocols (e.g., PCIe, HBM, DDR5, UCIe, Ethernet), with EDA waveform debug tools (e.g., Verdi, SimVision/Indago, GDB) and CI/CD regression automation.\nExperience with Verilog/SystemVerilog and coding or scripting in C/C++, Perl/TCL, or Python.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.\nExperience interfacing with emulation EDA vendors and internal infrastructure teams to triage complex compiler, tool, and platform issues and scale emulation throughput.\nExperience across three or more SoC projects/tapeout cycles.\nUnderstanding of RTL to Emulation/FPGA flows including Emulation test benches (e.g., Transactors/Accelerated VIPs, Hybrid, In-circuit Emulation).","description_format":"text","description_chars":4578,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Digital Media","Marketing Analytics & Attribution","Streaming & OTT Platforms","Consumer Internet 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