{"id":1897520,"url":"https://alion.io/job/google-senior-performance-co-design-engineer-google-cloud-tpu","title":"Senior Performance Co-Design Engineer, Google Cloud TPU","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":114,"ghost_share":0,"stale_share":0.982,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":145000,"max_usd":271000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1211},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Edge AI","optional":false},{"name":"GCP","optional":false},{"name":"LLM","optional":false},{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"TPU","optional":false},{"name":"Vertex AI","optional":false}],"status":"live","first_seen_at":"2026-10-05T06:39:49Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-13T22:55:08Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"About the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.The Tensor Processing Unit (TPU) Chip Architecture and Performance Codesign team is at the forefront of optimizing Google's custom AI silicon for next-generation machine learning models.\nAs a Senior Performance Co-Design Engineer, you will focus on analyzing and optimizing the serving performance of emerging models and use cases on our custom hardware. You will also work closely with hardware architects to influence the evolution of Google’s custom ML accelerators.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\n Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nConduct comprehensive serving performance studies on current and emerging first-party and third-party LLMs.\nDevelop and maintain advanced simulation, profiling, and modeling tools to identify bottlenecks, understand key characteristics, and project serving workload performance.\nPartner with model researchers, software teams, and hardware teams to co-design architectural improvements tailored to Large Language Model (LLM) inference latency and throughput.\nDrive data-backed decisions that influence the roadmap for future TPU and Cloud Silicon architectures.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\n8 years of experience in performance modeling/engineering, computer architecture, codesign, or systems engineering.\nExperience programming in C++ or Python.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.\nExperience with hardware/software co-design problems, especially performance analysis and identification at the pre-silicon stage.\nExperience enabling and optimizing ML models (e.g., LLMs, large embedding models).\nExperience with ML infrastructure, profiling tools, or deep learning inference/serving optimizations.\nFamiliarity with accelerator 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