{"id":1237938,"url":"https://alion.io/job/google-senior-physical-design-engineer-fullchipasic-implementation","title":"Senior Physical Design Engineer, FullChip/ASIC Implementation","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Mountain View, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":128000,"max_usd":237000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":700},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-23T11:08:44Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-09-26T21:50:13Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nDevelop all aspects of ASIC Register Transfer Level to Graphic Data System (RTL2GDS) implementation for high Power, Performance, and Area (PPA) designs.\nManage full-chip level physical implementation.\nDefine and implement innovative schemes to improve Performance and Power.\nWork with cross functional teams to deliver best Quality of results.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering or equivalent practical experience.\n8 years of physical design experience\nExperience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).\nExperience in high performance synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.\nPreferred qualifications:\nExperience in top-level floorplanning, block integration.\nExperience in low power design Implementation including UPF/CPF, multi-voltage domains, power gating.\nExperience with ASIC design flows and methodology of Physical design.\nKnowledge of fundamentals of computer architecture and of Verilog/SystemVerilog.\nUnderstanding of Circuit design, device physics and deep submicron technology.\nExceptional skills with scripting languages such as Tcl, or Perl.","description_format":"text","description_chars":2189,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Streaming & OTT Platforms","Foundation Models","Consumer Internet Groups"],"lifecycle":[{"event":"open","at":"2026-09-25T16:14:42Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":2,"expected_fill_days":30,"reasons":["conf:3","velocity","win:early","comp:brand"],"computed_at":"2026-09-26T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/google-senior-physical-design-engineer-fullchipasic-implementation","json_url":"https://alion.io/job/google-senior-physical-design-engineer-fullchipasic-implementation.json","meta":{"generated_at":"2026-09-27T02:16:13Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2042,"day_limit":5000,"remaining_today":2958,"minute_limit":60,"resets_at":"2026-09-28T00:00:00Z"}}}