{"id":2468009,"url":"https://alion.io/job/google-senior-staff-cpu-cache-subsystem-design-engineer","title":"Senior Staff CPU Cache Subsystem Design Engineer","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":116,"ghost_share":0,"stale_share":0.983,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-14T06:34:16Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":115000,"max_usd":229000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1158},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-10-13T16:08:54Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-14T08:09:29Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.\nIn this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into target SOCs.\nYou will lead a front-end design team, collaborate with members of architecture, software, verification, power, DFT, physical design teams to define the microarchitecture and schedule in delivering high quality RTL that meets project goals.\nYou'll help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options with complexity, performance, power and area and schedule in mind.\nGoogle's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.\nIndividual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nLead a team of digital design engineers working on CPU functional units, focusing specifically on microarchitecture and RTL design for next-generation CPU subsystems.\nReview and propose performance-enhancing microarchitecture features while collaborating closely with cross-functional software, architecture, and performance teams on trade-off studies.\nDeliver comprehensive plans to achieve project milestones and execution goals, ensuring the production-quality design meets strict scheduling targets.\nCollaborate directly with verification, physical design, and power analysis teams to ensure designs successfully meet frequency, power, and area targets.\nDirect load-store unit and cache subsystem design optimizations across CPU components to deliver power, performance, and area metrics.\nQualifications\nMinimum qualifications:\nMaster’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.\n15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including microarchitecture definition and PPA optimizations.\nExperience leading technical teams for modern processor subsystems with high speed, lower power design.\nExperience with front-end quality checks (e.g., Lint, CDC/RDC).\nPreferred qualifications:\nExperience with ARM instruction set architecture.\nExperience with mobile CPU subsystem.\nExperience with mobile SOC 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