{"id":1277887,"url":"https://alion.io/job/google-senior-staff-performance-codesign-engineer-tpu","title":"Senior Staff Performance Codesign Engineer, TPU","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":111,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-06T05:45:30Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":128000,"max_usd":257000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1026},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Edge AI","optional":false},{"name":"GCP","optional":false},{"name":"Machine Learning","optional":false},{"name":"Outlook","optional":false},{"name":"TPU","optional":false},{"name":"Vertex AI","optional":false},{"name":"PyTorch","optional":true},{"name":"TensorFlow","optional":true}],"status":"live","first_seen_at":"2026-09-15T15:38:51Z","employer_posted_date":"2026-10-04","last_verified_at":"2026-10-06T20:17:04Z","board_verified":true,"closed_at":null,"days_open":21,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":21},"description":"About the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Senior Staff Co-Design Engineer on the TPU Chip Architecture team, you will bridge the gap between model architecture innovation and next-generation hardware design. Operating at the intersection of AI research and infrastructure engineering, you will define the long-term strategic outlook and architectural roadmap for our future machine learning training and serving capabilities. You will advocate the integration of foundational ML research-such as massive-scale frontier models-with advanced custom silicon architectures to deliver industry-defining, high-performance, and power-efficient accelerators.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nDefine and drive the technical roadmap and architecture for the hardware/software stack, ensuring unparalleled performance for the training and serving of large ML models.\nAct as the technical liaison between advanced research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency.\nArchitect and oversee the development of next-generation configurable simulation frameworks and cycle-accurate performance models, setting the standard for how the organization evaluates complex micro-architectural decisions.\nAdvocate system-level performance analysis across highly distributed ML systems, innovating new methodologies to balance compute, memory bandwidth, and inter-chip network requirements.\nManage cross-functional partnerships across hardware engineering, compiler development, and ML research to influence broad organizational strategy and transition paradigm-shifting concepts into production.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.\n12 years of experience in computer architecture, chip architecture, or hardware-software co-design.\nExperience developing systems for performance modeling, simulation, or system analysis.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.\nExperience as a lead architect driving multi-generational hardware solutions or performance optimizations for massive-scale ML training and inference.\nExperience with deep learning frameworks (e.g., PyTorch, TensorFlow) and their underlying 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