Signal and Power Integrity Engineer

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Signal Integrity/Power Integrity Engineer, you will lead chip and package design, ensuring optimal SI/PI performance and system co-design from concept to production. Collaborating within a cross-functional team, including Chip Design, IP, System Design, software, and vendors, you will drive signal and power design implementations on chip and advanced packages.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Lead signal integrity (SI) and power integrity (PI) analysis and optimization for High-Performance Computing (HPC) leveraging advanced 2.5D/3D packaging technologies.
• Partner early in product definition to influence chip floorplanning, power distribution networks (PDN/power trees), netlists, and routability tradeoffs.
• Evaluate high-speed interface IPs and develop next-generation memory interfaces across IO PHY, SI/PI, and physical design boundaries.
• Drive post-silicon validation and qualification for NPI, balancing SI/PI performance and DFM constraints to achieve final package design closure.
• Partner closely with silicon, system, and external vendor teams while developing simulation methodologies to boost modeling accuracy and efficiency.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in SI/PI design for chip/package or system PCB.
• Experience in industry SIPI modeling tool chains e.g., HFSS, ADS, Sigrity, Siwave, etc.
• Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes.
• Experience with partnering across chip architecture, physical design, static timing analysis (STA), package, and validation teams.
• Experience in Python, MATLAB, or C++ to establish automated flows and data processing tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Deep knowledge of SI/PI analysis for high-speed interconnects (HBMx, D2D/chiplets, PCIe, SerDes) and timing budget methodologies.
• Direct experience with silicon interposers, silicon bridges, and 3D die stacking architectures.