Silicon Hardware Emulation Engineer, Google Cloud

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will help develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our ASIC projects. You will help create ASICs representing a significant investment in time and money, and a successful prototyping campaign helps to ensure success of these critical projects. However, as designs continue to increase in size and complexity, emulation becomes even more important in meeting verification and bring-up milestones. You will provide excellent emulation infrastructure and methodologies essential to support these projects.

You will work directly with other emulation team members as well as designers, verification engineers, and software teams. You will interface with our external vendors, lab support teams, networking and security, and Electronic design automation (EDA) tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You may also assist in compiling projects targeting our prototyping platforms, debugging issues in both infrastructure and design, and assisting in the hardware and lab bring up and verification of our ASIC systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Help own, maintain and upgrade our emulation infrastructure and act as a primary interface to emulation vendors.
• Explore emulation methodologies, gather feedback from the team and implement new emulation workflows and methodologies.
• Support emulation team members in debug of hardware, tooling, and project specific issues, as well as software team members in running and debugging tests and performing functional validation on emulation platforms.
• Bring up external interfaces (e.g., Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), or Ethernet on the emulation platforms and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of industry experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).
• Experience with coding or scripting in C, C++, Perl, TCL or Python.
• Experience with emulation systems (e.g., ZeBu, Palladium, Veloce), compilation, debugging, performance and methodology enhancements.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).
• Experience with performance analysis/debug techniques.
• Knowledge of external input/output (I/O) interfaces, such as Peripheral Component Interconnect Express (PCIe), Double Data Rate 5 (DDR5), High Bandwidth Memory (HBM), Serial Peripheral Interface (SPI), or Joint Test Action Group (JTAG).
• Understanding of computer architecture including industry standard interfaces and memory subsystems.