{"id":1278126,"url":"https://alion.io/job/google-silicon-physical-design-engineer","title":"Silicon Physical Design Engineer","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":92,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":44000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":536},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"closed","first_seen_at":"2026-09-11T15:13:30Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-30T04:49:33Z","board_verified":false,"closed_at":"2026-09-30T04:49:33Z","days_open":18,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":18},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Application Instructions: In most instances, this position requires in-person interviews as part of the hiring process.\nAs a Physical Design Engineer, you will contribute to improving Design Power, Performance, and Area (PPA) using various techniques. You will use your experience of physical design and machine learning to solve hard technical problems, collaborate with Register-Transfer Level/Design Verification/Design for Testability (RTL/DV/DFT) teams, and improve on Power, Performance, Area and Schedule. You will directly impact logic design and optimizations, floorplan, place and route, clock and power planning, timing analysis, Power Distribution Network (PDN) analysis and beyond. You will collaborate across Alphabet working with design, CAD and machine learning teams.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.\nResponsibilities\nTake end-to-end ownership of synthesis-to-Graphic Data System (GDS) implementation of complex physical partitions/subsystems.\nCollaborate with sign-off teams and own the convergence of Electromigration (EM)/IR, power, timing and physical verification.\nCollaborate with cross-functional teams RTL, DFT, CAD to improve Power/Performance/Area in physical design.\nUse and improve CAD recipes for PPA benefits.\nQualifications\nMinimum qualifications:\n Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\n4 years of experience in physical design.\nExperience in high performance synthesis, Place and Route (PnR) and sign-off optimizations. Experience in sign-off convergence, including Static Timing Analysis (STA), electrical checks and physical verification.\nExperience with programming in TCL/Python.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.\nExperience with constraints, synthesis or Clock Tree Synthesis (CTS).\nExperience using Machine Learning (ML) in physical design/signoff convergence (e.g., STA/EMIR closure).\nKnowledge of Verilog/SystemVerilog.\nUnderstanding of circuit design, device physics and deep submicron technology.","description_format":"text","description_chars":2963,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Streaming & OTT Platforms","Foundation Models","Consumer Internet Groups"],"lifecycle":[{"event":"open","at":"2026-09-26T02:15:01Z"},{"event":"close","at":"2026-09-30T04:49:33Z"}],"liveness":null,"pay":null,"html_url":"https://alion.io/job/google-silicon-physical-design-engineer","json_url":"https://alion.io/job/google-silicon-physical-design-engineer.json","meta":{"generated_at":"2026-10-02T01:38:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2073,"day_limit":5000,"remaining_today":2927,"minute_limit":60,"resets_at":"2026-10-03T00:00:00Z"}}}