{"id":2644423,"url":"https://alion.io/job/google-soc-and-ip-design-engineer-google-cloud-2","title":"SOC and IP Design Engineer, Google Cloud","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":114,"ghost_share":0,"stale_share":0.982,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Haifa, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":80000,"max_usd":186000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":723},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"GCP","optional":false},{"name":"Gemini","optional":false},{"name":"Machine Learning","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TPU","optional":false},{"name":"Verilog","optional":false},{"name":"Vertex AI","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-10-15T12:42:29Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-18T14:21:41Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.\nWe prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.\nResponsibilities\nDefine the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).\nPerform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.\n\nParticipate in synthesis, timing/power closure activities.\nParticipate in test plan and coverage analysis of the block and SoC-level verification.\n\nCommunicate and work with multi-disciplined and multi-site teams.\n\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\n4 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.\nExperience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.\nExperience with design sign-off and quality tools (e.g., Lint, CDC, etc.).\nExperience with SoC or IP architecture.\n\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.\nKnowledge of high-performance and low-power design techniques, assertion-based formal verification, Field-programmable Gate Array (FPGA) and emulation platforms, and SoC architecture.\nKnowledge in one of the following areas such as Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), High-bandwidth memory (HBM).\nExcellent problem-solving and debugging skills.","description_format":"text","description_chars":2664,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Digital Media","Marketing Analytics & Attribution","Streaming & OTT Platforms"],"lifecycle":[{"event":"open","at":"2026-10-15T19:36:42Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":1,"expected_fill_days":30,"reasons":["conf:2","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/google-soc-and-ip-design-engineer-google-cloud-2","json_url":"https://alion.io/job/google-soc-and-ip-design-engineer-google-cloud-2.json","meta":{"generated_at":"2026-10-18T16:43:50Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22225,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":82},"rest":"https://alion.io/mcp/rest/get_company?id=82"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fgoogle-soc-and-ip-design-engineer-google-cloud-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fgoogle-soc-and-ip-design-engineer-google-cloud-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fgoogle-soc-and-ip-design-engineer-google-cloud-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/google-soc-and-ip-design-engineer-google-cloud-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fgoogle-soc-and-ip-design-engineer-google-cloud-2"}]}