{"id":3396446,"url":"https://alion.io/job/google-soc-constraints-design-engineer-silicon","title":"SoC Constraints Design Engineer, Silicon","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":81,"open_postings":152,"ghost_share":0.046,"stale_share":0.632,"repost_share":0.046,"time_to_fill_p50_days":30,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17500,"max_usd":40000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":843},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":true}],"status":"live","first_seen_at":"2026-10-28T09:39:21Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-10-30T22:06:23Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"About the job\nBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.\nGoogle Silicon is developing custom silicon solutions that power the future of Google's direct-to-consumer products, including Pixel and other devices. We combine the best of Google's Artificial Intelligence (AI), Software, and Hardware to create radically helpful experiences.\nIn this role, you will be part of a team that pushes boundaries, shaping the next generation of hardware experiences by delivering unparalleled power, performance, area efficiency, and integration. You will be part of Google’s Silicon team, developing hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuits (ASIC). You will drive the complete design constraints development, its validation, working on sign-off timing convergence for designs including deciding the initial timing goals, setting up the timing analysis flows and methodology, and working with the implementation engineers to hit the timing goals.\nThe Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.\nResponsibilities\nCollaborate with Architecture/Microarchitecture/ Register-Transfer Level (RTL) design teams to capture timing intent, and drive timing convergence.\nLead the development and validation of Synopsys Design Constraints (SDC) for complex System on a Chip (SoC) subsystems and top-level integration from architecture/microarchitecture documents that gets used in static timing analysis as well as physical design implementation.\nUnderstand clocking structures and Clock Domain Crossing (CDC) strategies to ensure robust timing across all functional and test modes.\nDesign constraints validation across multiple corners/modes using Fishtail/Timevision.\nWork closely with the design team and block owners throughout the project for sign-off timing convergence. Constraints promotion and demotion flow using fishtail, timevision.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\n4 years of experience with digital logic design principles, RTL design concepts.\n1 year of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology scaling and Process Design Kit (PDK) changes.\nExperience with scripting languages (e.g., Python, Perl, Tcl) to automate workflows, parse electronic design automation (EDA) reports, and develop custom utilities.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.\nExperience in developing constraints and validating the same using Timing Constraints Manager (e.g., Synopsys)/TimeVision (e.g., Ausdia).\nExperience with liberty timing models and Static Timing Analysis tools (e.g., TCM/TimeVision, Primetime, Tempus).\nUnderstanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking, and power management.\nUnderstanding of various external Input/Output (IO) protocols.","description_format":"text","description_chars":3842,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Internet Services","Digital Storage","Digital Media"],"lifecycle":[{"event":"open","at":"2026-10-28T12:37:36Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":1,"expected_fill_days":30,"reasons":["conf:3","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/google-soc-constraints-design-engineer-silicon","json_url":"https://alion.io/job/google-soc-constraints-design-engineer-silicon.json","meta":{"generated_at":"2026-10-31T02:14:55Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3131,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-01T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":82},"rest":"https://alion.io/mcp/rest/get_company?id=82"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fgoogle-soc-constraints-design-engineer-silicon"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fgoogle-soc-constraints-design-engineer-silicon"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fgoogle-soc-constraints-design-engineer-silicon"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/google-soc-constraints-design-engineer-silicon\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fgoogle-soc-constraints-design-engineer-silicon"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3396446}},{"tool":"search_jobs","arguments":{"company":"google.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3396446},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); 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