SoC Product Engineer, Google Cloud
Confirmed on the employer's own hiring board on Oct 19, 2026. First seen by Alion on Oct 19, 2026. Google scores B on the Alion truth index.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google’s data centers are the most advanced in the world. In this role, you will help to manufacture the SoC’s that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and OSAT’s. This is an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips.
In this role, you will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will have an understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality targets.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
- Drive interactions with wafer fabs and OSATs, own and drive checkpoints for key quality metrics.
- Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and Return Merchandise Authorization (RMA) handling.
- Own setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support.
- Collaborate with cross-functional teams across the globe including ATE and SLT Test Engineering, Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with industry-standard tools, languages and methodologies relevant to the production Silicon SoC’s or ASIC’s, including product engineering or test engineering.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with leadership delivering HVM screening solutions for high-performance computing chips in advanced technology nodes with low DPPM.
- Experience evaluating customer returns with ATE and SLT, identifying coverage gaps, developing incremental structural and functional patterns to address quality issues.
- Experience with industry standards, design tools, and DFT best practices, including at-speed TDF, ATPG, MBIST, Memory Repair, diagnostic tools, yield improvement.
Experience in Python/Perl for data automation, statistical analysis (e.g., JMP), and yield management systems (e.g., Exensio, YieldExplorer).