{"id":4026275,"url":"https://alion.io/job/google-staff-cad-engineer-silicon-design-google-cloud-2","title":"Staff CAD Engineer, Silicon Design, Google Cloud","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":78,"open_postings":132,"ghost_share":0.045,"stale_share":0.75,"repost_share":0.045,"time_to_fill_p50_days":30,"computed_at":"2026-11-10T06:52:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"GCP","optional":false},{"name":"Python","optional":false},{"name":"TPU","optional":false},{"name":"Vertex AI","optional":false}],"status":"live","first_seen_at":"2026-11-10T12:41:00Z","employer_posted_date":"2026-11-10","last_verified_at":"2026-11-10T22:20:46Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"About the job\nIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.\nAs a Staff CAD Engineer, Silicon Design Environment, you will collaborate closely with domain experts across the silicon development spectrum and leverage your experience to deliver the development environment that enables building the chips powering the next-generation of Google Cloud systems. You possess excellent communication and collaboration skills, expertise in refining ambiguous intent into engaging solutions, and rally others to develop or deploy them.\nThe AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.\nWe're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.\n Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits\nLearn more about benefits at Google.\nResponsibilities\nLeverage the understanding of the phases of silicon development to flesh out the architecture and lead development and deployment of the overall CI2 design environment as a coherent system composed of first-party and third-party tools, industry-standard and Google-specific APIs/data formats and the scalable design flows.\nCollaborate with technical leaders across CI2 sites to identify opportunities for evolutionary and revolutionary tooling and methodology changes to enable convergence on a shared design environment.\nEngage with other Alphabet teams, DeepMind, and Core teams to ensure CI2 stays at the forefront of advanced silicon development.\nEnsure developed technologies optimize for project iteration speed while achieving the planned power, performance, cost, and quality metrics.\nPartner with other members of the tools and methodologies team to apply procedural and AI-first approaches to improve efficiency.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.\n10 years of experience in technical leadership focusing on one or more critical aspects of silicon design.\nExperience in two or more silicon disciplines, including architecture modeling, logic design, functional verification, DFT, synthesis, place and route, timing analysis, physical verification, or firmware development.\nExperience in developing, and deploying advanced tools and development flows that streamline the silicon life-cycle and improve engineering productivity.\nExperience with developing tools in one or more programming languages such as Python or C/C++.\nPreferred qualifications:\nMaster's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.\n15 years of relevant academic and industrial experience in advanced silicon development.\n\nExperience in identifying the need for a silicon methodology change, developing a solution, and successfully deploying it with impact to more than 25 developers.\nExperience in developing solutions that require bridging knowledge gaps amongst collaborators.\nExperience collaborating in internal company or external ecosystem standardization efforts.\nKnowledge of both front-end (architecture, logic design, verification) and back-end (logic synthesis, place-and-route, timing convergence, physical verification) silicon development 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