Staff Design Engineer, Networking, Google Cloud

About the job

In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.

The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Lead an ASIC subsystem.
• Understand how it interacts with software and other ASIC subsystems to implement data center networks.
• Define hardware/software interfaces. Write micro architecture and design specifications.
• Define efficient micro-architecture and block partitioning/interfaces and flows.
• Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Qualifications

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience architecting networking ASICs from specification to production.
• Experience developing Register-Transfer Level (RTL) for ASIC subsystems.
• Experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

• Experience working with software teams optimizing the hardware/software interface.
• Experience architecting networking switches, end points, and hardware offloads.
• Experience working with design networking like: remote direct memory access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
• Experience in transmission control protocol (TCP), IP, ethernet, peripheral component interconnect express (PCIE) and dynamic random access memory (DRAM) including network on chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI).
• Proficiency in procedural programming language (e.g., C++, Python, Go).
• Understanding of packet classification, processing, queuing, scheduling, switching, traffic conditioning, and telemetry.