{"id":1277994,"url":"https://alion.io/job/google-staff-rtl-ipcomponent-design-engineer-google-cloud","title":"Staff RTL IP/Component Design Engineer, Google Cloud","company":{"id":82,"name":"Google","domain":"google.com","url":"https://alion.io/company/google","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":117,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-09-27T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tel Aviv, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":130000,"max_usd":264000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":316},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Chisel","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-15T08:39:16Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-26T21:50:13Z","board_verified":true,"closed_at":null,"days_open":12,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":12},"description":"About the job\nIn this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.\nBehind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.\nResponsibilities\nDefine the block level design document such as interface protocol, block diagram, transaction flow and pipeline, etc.\nPerform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks.\nSupport synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.\nParticipate in test plan and coverage analysis of the block and SOC-level verification.\nCommunicate and work with multi-disciplined and multi-site teams.\nQualifications\nMinimum qualifications:\nBachelor's degree in Electrical Engineering or equivalent practical experience.\nExperience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).\nExperience in ASIC development with Verilog/SystemVerilog, VHDL or Chisel.\nExperience with System on a Chip (SoC) development cycles.\nPreferred qualifications:\nProficiency with a scripting language (e.g., Python or Perl).\nKnowledge of high performance and low power design techniques.\nKnowledge of assertion-based formal verification.\nKnowledge of FPGA and emulation platforms.\nKnowledge of SOC architecture.\nKnowledge in one of these areas: arithmetic units, bus architectures, processor design, accelerators or memory hierarchies.","description_format":"text","description_chars":2293,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Streaming & OTT Platforms","Foundation Models","Consumer Internet Groups"],"lifecycle":[{"event":"open","at":"2026-09-26T02:15:01Z"}],"liveness":{"score":30,"band":"fade","label":"Fading","p_open":1,"p_active":0.332,"p_room":0.9,"age_days":11,"expected_fill_days":30,"reasons":["conf:7","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-09-27T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/google-staff-rtl-ipcomponent-design-engineer-google-cloud","json_url":"https://alion.io/job/google-staff-rtl-ipcomponent-design-engineer-google-cloud.json","meta":{"generated_at":"2026-09-28T01:53:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1038,"day_limit":5000,"remaining_today":3962,"minute_limit":60,"resets_at":"2026-09-29T00:00:00Z"}}}