TPU RTL Design Engineer, Google Cloud
Confirmed on the employer's own hiring board on Oct 1, 2026. First seen by Alion on Sep 30, 2026. Google scores B on the Alion truth index.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a SoC Design Engineer, you will join a team working on SoC-level RTL design for our data center accelerators. You will design RTL IP with the focus on chassis infrastructure, including fabric bridges and sensor telemetry network, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., error handling, debug, chip management and SOC chassis, etc.). You will build a global understanding of how our accelerators are built from concept to production. This is a highly cross-functional role that will require you to coordinate and co-design with our software and system hardware counterparts. In this role, you will utilize a background in RTL design and lead multi-faceted efforts involving many stakeholders.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Work independently to create and review clock control subsystem's design micro-architecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with architecture and power teams to evaluate features and their impact.
- Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
Qualifications
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 2 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development.
- Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
- Experience using Python, Tcl, or Perl for automating design tasks and data analysis.
- Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of experience with high-performance ASIC design in Phase-Locked Loop, Frequency-Locked Loop, and Delay-Locked Loop integration.
- Experience implementing clock skipping, Dynamic Voltage and Frequency Scaling (DVFS), and fine-grained clock gating for low-power SoC optimization.
- Knowledge of processor design or accelerators and of high-performance and low power design techniques.
- Understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion.
- Proficiency in Python or Perl for automating design scripts and analyzing complex clock-tree data.