{"id":2503693,"url":"https://alion.io/job/grovf-senior-haps-zebu-emulation-engineer","title":"Senior HAPS / ZeBu Emulation Engineer","company":{"id":3791252,"name":"Grovf","domain":"grovf.com","url":"https://alion.io/company/grovf","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Spark","truth_index":{"grade":"B","score":75,"open_postings":7,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Armenia"],"countries":["AM"],"hiring_countries":["AM"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":63000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1777},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Git","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"Siemens Veloce","optional":false},{"name":"Synopsys HAPS","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"Synopsys ZeBu","optional":false},{"name":"Synplify Pro","optional":false},{"name":"SystemVerilog","optional":false},{"name":"TCL Scripting","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-04-14T00:00:00Z","employer_posted_date":"2026-04-14","last_verified_at":"2026-10-23T12:17:33Z","board_verified":true,"closed_at":null,"days_open":192,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":192},"description":"About Grovf\nGrovf is seeking a skilled Senior HAPS/ZeBu Emulation Engineer to join our team. Our work environment is dynamic, educational, and challenging, offering employees the opportunity to contribute to the development of next-generation networking devices for Next generation AI Infrastructure that lead the industry in performance and power efficiency. As part of the team, you will be involved in all stages of ASIC development, including Micro-Architecture, Design, and Verification. Our collaborative environment fosters growth, innovation, and leadership, offering the opportunity to work alongside industry experts and contribute to groundbreaking advancements.\nAt Grovf, every individual plays a vital role in the company's success. If you're looking for a rewarding career, talented colleagues, and a great environment that fosters growth, challenges, and leadership, Grovf is the place for you.\nRole Overview\nWe are looking for an experienced emulation engineer to drive pre-silicon validation of our next-generation AI datacenter networking ASICs using the Synopsys ZeBu emulation platform. You will own bring-up, compilation, and debug of complex SoC designs, working closely with RTL, DV, and software teams to enable early software development and system-level verification before tape-out.\nCore Technical Requirements\nSynopsys HAPS platform\nHands-on experience with HAPS (ZeBu) or ProtoCompiler\nDesign partitioning across multiple FPGAs\nHAPS-specific timing analysis & closure\nInterface board and daughter card setup\nHAPS Debug Link / virtual I/O familiarity\nFPGA implementation\nFamiliarity with FPGA-backed emulation internals\nRTL synthesis and place-and-route concepts\nClock domain crossing (CDC) management\nTiming constraints & closure fundamentals\nFPGA resource optimization awareness\nSoC / RTL knowledge\nSystemVerilog / Verilog RTL reading & debug\nComplex SoC architecture understanding\nHigh-speed interfaces: PCIe, Ethernet, HBM, DDR\nOn-chip interconnects (AXI, CHI, TileLink)\nIP integration and wrapper development\nPre-silicon verification\nSoftware bring-up on emulator (bare-metal & OS)\nCo-emulation and hybrid simulation flows\nBug reproduction from simulation to emulation\nRegression and stability testing on platform\nPerformance profiling on emulation model\nNetworking ASIC Domain Knowledge\nAI datacenter networking\nHigh-speed Ethernet (400G/800G) architecture\nPacket processing pipeline concepts\nNetwork-on-chip (NoC) structures\nTraffic manager & QoS logic\nSoftware & driver bring-up\nLinux kernel / driver development on emulator\nFirmware and bootloader bring-up\nPCIe enumeration and configuration space\nMemory map validation and BAR setup\nTools & Flows\nSynopsys ZeBu · Synopsys HAPS / ProtoCompiler · VCS / Xcelium · Verdi / DVE · Synplify Pro · SystemVerilog · Python / Tcl scripting · Git / Perforce · JTAG /ChipScope\nExperience & Education\nRequired\n5+ years in FPGA emulation or ASIC prototyping roles\nDirect hands-on ZeBu or HAPS platform experience\nInvolvement in pre-silicon bring-up of complex SoC designs\nBS in EE, CE, or Computer Science\nPreferred\nMS in relevant engineering discipline\nExperience with networking or switch ASICs\nFamiliarity with other emulation platforms (Palladium, Veloce)\nBackground in AI/ML accelerator silicon\nWhat Makes You Standout\nRDMA / RoCE and UEC protocol familiarity\nEnabled SW team 6+ months before tape-out\nDebugged a complex multi-domain boot failure\nAutomated emulation regression flows end-to-end\nCaught critical silicon bugs pre-tape-out on emulator\nWorked fluidly across RTL, DV, and SW teams\nYerevan, Armenia\nFull-time\nOn-site / Remote flexibility\nIf you want to play a key role in enabling pre-silicon software and system validation for next-generation AI networking ASICs, we’d love to hear from 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